WE310F5  39.00.000
m2mb_spi_slave.h
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1 /*===============================================================================================*/
2 /* >>> Copyright (C) Telit Communications S.p.A. Italy All Rights Reserved. <<< */
28 #ifndef M2M_M2MB_SPI_API_H
29 #define M2M_M2MB_SPI_API_H
30 
31 /* Global declarations ==========================================================================*/
32 #ifndef NULL
33 #define NULL 0
34 #endif
35 
36 /* Global enums ==============================================================================*/
37 
39 {
40  M2MB_SPI_IOCTL_SET_CFG = 0, /* set whole spi device configuration */
41  M2MB_SPI_IOCTL_GET_CFG, /* get whole spi device configuration */
42  M2MB_SPI_IOCTL_SET_SHIFT_MODE, /* set spi device shift mode */
43  M2MB_SPI_IOCTL_GET_SHIFT_MODE, /* get spi device shift mode */
44  M2MB_SPI_IOCTL_SET_CS_POLARITY, /* set spi device CS polarity */
45  M2MB_SPI_IOCTL_GET_CS_POLARITY, /* get spi device CS polarity */
46  M2MB_SPI_IOCTL_SET_CS_MODE, /* set spi device CS mode */
47  M2MB_SPI_IOCTL_GET_CS_MODE, /* get spi device CS mode */
48  M2MB_SPI_IOCTL_SET_BYTE_ORDER, /* set spi device endianness */
49  M2MB_SPI_IOCTL_GET_BYTE_ORDER, /* get spi device endianness */
50  M2MB_SPI_IOCTL_SET_CALLBACK_FN, /* set spi device callback function */
51  M2MB_SPI_IOCTL_GET_CALLBACK_FN, /* get spi device callback function */
52  M2MB_SPI_IOCTL_SET_CALLBACK_CTXT, /* set spi device callback context */
53  M2MB_SPI_IOCTL_GET_CALLBACK_CTXT, /* get spi device callback context */
54  M2MB_SPI_IOCTL_SET_CLK_FREQ_HZ, /* set spi device clock frequency in Hz */
55  M2MB_SPI_IOCTL_GET_CLK_FREQ_HZ, /* get spi device clock frequency in Hz */
56  M2MB_SPI_IOCTL_SET_BITS_PER_WORD, /* set spi device bits per word */
57  M2MB_SPI_IOCTL_GET_BITS_PER_WORD, /* get spi device bits per word */
58  M2MB_SPI_IOCTL_SET_CS_CLK_DELAY_CYCLES, /* set spi device cs_clk_delay_cycles */
59  M2MB_SPI_IOCTL_GET_CS_CLK_DELAY_CYCLES, /* get spi device cs_clk_delay_cycles */
60  M2MB_SPI_IOCTL_SET_INTER_WORD_DELAY_CYCLES, /* set spi device inter_word_delay_cycles */
61  M2MB_SPI_IOCTL_GET_INTER_WORD_DELAY_CYCLES, /* get spi device inter_word_delay_cycles */
62  M2MB_SPI_IOCTL_SET_LOOPBACK_MODE, /* set spi device loopback mode */
63  M2MB_SPI_IOCTL_GET_LOOPBACK_MODE, /* get spi device loopback mode */
64  M2MB_SPI_IOCTL_NOF_REQ /* number of m2mb ioctl requests */
65 };
66 
67 /* Global typedefs ==============================================================================*/
68 
69 /* SPI phase type.
70  This type defines the clock phase that the client can set in the
71  SPI configuration.
72 */
73 typedef enum
74 {
75  M2MB_SPI_MODE_0, /* CPOL = 0, CPHA = 0 */
76  M2MB_SPI_MODE_1, /* CPOL = 0, CPHA = 1 */
77  M2MB_SPI_MODE_2, /* CPOL = 1, CPHA = 0 */
78  M2MB_SPI_MODE_3, /* CPOL = 1, CPHA = 1 */
79  M2MB_SPI_MODE_INVALID = 0x7FFFFFFF
81 
82 /* SPI chip select polarity type.
83 */
84 typedef enum
85 {
86  M2MB_SPI_CS_ACTIVE_LOW, /* During Idle state, the CS line is held low */
87  M2MB_SPI_CS_ACTIVE_HIGH, /* During Idle state, the CS line is held high */
90 
91 /* SPI chip select assertion type.
92  This type defines how the chip select line is configured between N word cycles.
93 */
94 typedef enum
95 {
96  M2MB_SPI_CS_DEASSERT, /* CS is deasserted after transferring data for N clock cycles */
97  M2MB_SPI_CS_KEEP_ASSERTED, /* CS is asserted as long as the core is in the Run state */
100 
101 /* Order in which bytes from Tx/Rx buffer words are put on the bus.
102 */
103 typedef enum
104 {
105  M2MB_SPI_NATIVE = 0, /* Native */
106  M2MB_SPI_LITTLE_ENDIAN = 0, /* Little Endian */
107  M2MB_SPI_BIG_ENDIAN /* Big Endian (network) */
109 
110 typedef enum
111 {
114 
115 typedef void ( *m2mb_spi_ind_callback )( INT32 fd, M2MB_SPI_IND_E spi_event, UINT16 resp_size, void *resp_struct, void *userdata );
116 
117 /* SPI configuration.
118  The SPI configuration is the collection of settings specified for each SPI
119  transfer call to select the various possible SPI transfer parameters.
120 */
121 typedef struct
122 {
123  M2MB_SPI_SHIFT_MODE_T spi_mode; /* Shift mode */
124  M2MB_SPI_CS_POLARITY_T cs_polarity; /* CS polarity */
125  M2MB_SPI_CS_MODE_T cs_mode; /* CS mode */
126  M2MB_SPI_BYTE_ORDER_T endianness; /* Endianness */
127  m2mb_spi_ind_callback callback_fn; /* Callback function; if NULL, transfer operates in synchronous mode */
128  HANDLE callback_ctxt; /* Pointer to a client object that will be returned as an argument to callback_fn */
129  UINT32 clk_freq_Hz; /* Host sets the SPI clock frequency closest (>=) to the requested frequency. Must be at least 960000 */
130  UINT8 bits_per_word; /* bits per word; any value from 3 to 31 */
131  UINT8 cs_clk_delay_cycles; /* Number of clock cycles to wait after asserting CS before starting transfer */
132  UINT8 inter_word_delay_cycles; /* Number of clock cycles to wait between SPI words */
133  BOOLEAN loopback_mode; /* Normally 0. If set, the SPI controller will enable Loopback mode;
134  used primarily for testing */
136 
137 /* Global functions =============================================================================*/
138 
139 /*-----------------------------------------------------------------------------------------------*/
140 /* m2mb_spi_open:
141  description:
142  open a SPI device
143  arguments:
144  path: /dev/spidevX.Y where
145  X is the HW SPI master instance index (from 1 to 6). Default is 5.
146  Y is the SPI slave device index. Default is 0.
147  Path "/dev/spidevX" is equivalent to default "/dev/spidevX.0"
148  Path "/dev/spidev" is equivalent to default "/dev/spidev5.0"
149  flags: currently unused
150  return:
151  file descriptor on SUCCESS
152  -1 on FAILURE
153  i.e.: fd = m2mb_spi_open( "/dev/spidev5.0", 0 );
154  note: SPI functionality works only if USIF1 port is not occupied. As a consequence, the customer should select a port variant that does not contemplate
155  an AT instance on USIF1 port .
156 */
157 INT32 m2mb_spi_open( const CHAR *path, INT32 flags, ... );
158 
159 /*-----------------------------------------------------------------------------------------------*/
160 /* m2mb_spi_close:
161  description:
162  close a SPI device
163  arguments:
164  fd: file descriptor returned by m2mb_spi_open
165  return:
166  0 on SUCCESS
167  -1 on FAILURE
168 */
170 
171 /*-----------------------------------------------------------------------------------------------*/
172 /* m2mb_spi_ioctl:
173  description:
174  configure a SPI device
175  arguments:
176  fd: file descriptor returned by m2mb_spi_open
177  request: required operation (see M2MB_SPI_IOCTL_REQUEST)
178  cfg_ptr: pointer to the set/get val, casted to void*
179  return:
180  0 on SUCCESS
181  -1 on FAILURE
182  i.e. m2mb_spi_ioctl(fd, M2MB_SPI_IOCTL_SET_CFG, (void *)&config)
183  where config is a M2MB_SPI_CFG_T struct
184  note: SPI functionality works only if USIF1 port is not occupied. As a consequence, the customer should select a port variant that does not contemplate
185  an AT instance on USIF1 port .
186 */
187 INT32 m2mb_spi_ioctl( INT32 fd, INT32 request, ... );
188 
189 /*-----------------------------------------------------------------------------------------------*/
190 /* m2mb_spi_read:
191  description:
192  read nbyte Bytes from a SPI device into the array pointed by buf
193  arguments:
194  fd: file descriptor returned by m2mb_spi_open
195  buf: destination buffer, previously allocated
196  nbyte: length of destination buffer in Bytes
197  returns:
198  number of read Bytes on SUCCESS
199  -1 on FAILURE
200 */
201 SSIZE_T m2mb_spi_read( INT32 fd, void *buf, UINT32 nbyte );
202 
203 /*-----------------------------------------------------------------------------------------------*/
204 /* m2mb_spi_write:
205  description:
206  write nbyte Bytes from the array pointed by buf to a SPI device
207  arguments:
208  fd: file descriptor returned by m2mb_spi_open
209  buf: source buffer, previously allocated
210  nbyte: length of source buffer in Bytes
211  returns:
212  number of written Bytes on SUCCESS
213  -1 on FAILURE
214 */
215 SSIZE_T m2mb_spi_write( INT32 fd, const void *buf, UINT32 nbyte );
216 
217 /*-----------------------------------------------------------------------------------------------*/
218 /* m2mb_spi_write_read:
219  description:
220  perform a bi-directional (full duplex) transfer.
221  Read nbyte Bytes from a SPI device into the buffer bufRd
222  and write nbyte Bytes from the buffer bufWr to a SPI device
223  arguments:
224  fd: file descriptor returned by m2mb_spi_open
225  bufWr: source buffer, previously allocated
226  bufRd: destination buffer, previously allocated
227  nbyte: length of source and destination buffers in Bytes
228  returns:
229  number of written/read Bytes on SUCCESS
230  -1 on FAILURE
231 */
232 SSIZE_T m2mb_spi_write_read( INT32 fd, const void *bufWr, void *bufRd, UINT32 nbyte );
233 
234 #endif /* M2M_M2MB_SPI_API_H */
235 
236 
INT32 SSIZE_T
Definition: m2mb_types.h:107
INT32 m2mb_spi_close(INT32 fd)
M2MB_SPI_BYTE_ORDER_T
SSIZE_T m2mb_spi_write_read(INT32 fd, const void *bufWr, void *bufRd, UINT32 nbyte)
M2MB_SPI_IND_E
Definition: m2mb_spi.h:121
unsigned char UINT8
Definition: m2mb_types.h:86
M2MB_SPI_SHIFT_MODE_T
M2MB_SPI_IOCTL_REQUEST
Definition: m2mb_spi.h:48
INT32 m2mb_spi_open(const CHAR *path, INT32 flags,...)
SSIZE_T m2mb_spi_read(INT32 fd, void *buf, UINT32 nbyte)
unsigned short UINT16
Definition: m2mb_types.h:87
UINT8 BOOLEAN
Definition: m2mb_types.h:95
char CHAR
Definition: m2mb_types.h:76
M2MB_SPI_BYTE_ORDER_T
Definition: m2mb_spi.h:114
M2MB_SPI_IND_E
INT32 m2mb_spi_ioctl(INT32 fd, INT32 request,...)
M2MB_SPI_CS_POLARITY_T
M2MB_SPI_SHIFT_MODE_T
Definition: m2mb_spi.h:84
M2MB_SPI_CS_MODE_T
unsigned long int UINT32
Definition: m2mb_types.h:88
signed int INT32
Definition: m2mb_types.h:82
SSIZE_T m2mb_spi_write(INT32 fd, const void *buf, UINT32 nbyte)
M2MB_SPI_CS_MODE_T
Definition: m2mb_spi.h:105
void * HANDLE
Definition: m2mb_types.h:98
M2MB_SPI_CS_POLARITY_T
Definition: m2mb_spi.h:95
void(* m2mb_spi_ind_callback)(INT32 fd, M2MB_SPI_IND_E spi_event, UINT16 resp_size, void *resp_struct, void *userdata)