31 #ifndef M2MB_SLAVE_SDIO_API_H 32 #define M2MB_SLAVE_SDIO_API_H 53 #define M2MB_SLAVE_WRITE_DONE_EVT (0x00000001) 54 #define M2MB_SLAVE_INIT_DONE_EVT (0x00000002) 56 #define M2MB_SDIO_SLAVE_RECEIVE_BUFFER_COUNT (16) 57 #define M2MB_SDIO_SLAVE_RECEIVE_BUFFER_SIZE (1536) 59 #define M2MB_NUM_BUFFERS_PER_MBOX (16) 61 #define M2MB_SDIO_SLAVE_WRITE_BUFFER_SIZE (2048) 63 #define M2MB_MBOX_BLOCK_SIZE 256 64 #define M2MB_MBOX_MSG_HDR_SIZE (2) 65 #define M2MB_MBOX_PAYLOAD_MAX_SIZE (M2MB_SDIO_SLAVE_RECEIVE_BUFFER_SIZE-M2MB_MBOX_MSG_HDR_SIZE) 67 #ifdef M2MB_TX_MULTIPLE_ENQ_ENABLE 68 #define M2MB_SDIO_SLAVE_WRITE_BUFFER_MAX ((M2MB_SDIO_SLAVE_WRITE_BUFFER_SIZE/M2MB_SDIO_SLAVE_RECEIVE_BUFFER_SIZE)+1) 70 #define M2MB_SDIO_SLAVE_WRITE_BUFFER_MAX (1) 74 #define M2MB_MBOX_MAX_TX_SIZE 256 76 #define M2MB_SDIO_SLAVE_FLOW_CTRL_LOW_THRESHOLD 6 77 #define M2MB_SDIO_SLAVE_FLOW_CTRL_HIGH_THRESHOLD 9 79 #define M2MB_SDIO_SLAVE_MBOX_ID (0) 82 typedef struct M2MB_SLAVE_SDIO_WRITE_REQUEST_S { 117 #ifdef M2MB_TX_MULTIPLE_ENQ_ENABLE 803 void *pInitCb,
void *pSendCb,
void *pRecvCb,
void *pContext);
CHAR rx_buffer[M2MB_SDIO_SLAVE_RECEIVE_BUFFER_COUNT][M2MB_SDIO_SLAVE_RECEIVE_BUFFER_SIZE]
struct M2MB_SLAVE_MBOX_MSG_S M2MB_SLAVE_MBOX_MSG_T
#define M2MB_SDIO_SLAVE_RECEIVE_BUFFER_SIZE
void m2mb_slave_sdio_deinit(int instance_id, int mbox)
stops mbox h/w and deallocates dma resources
M2MB_SLAVE_SDIO_BUFFER_T tx_buf_info[M2MB_SDIO_SLAVE_WRITE_BUFFER_MAX]
struct M2MB_OS_SEM_HANDLE_TAG * M2MB_OS_SEM_HANDLE
void m2mb_slave_sdio_post_init(UINT32 instance_id, INT32 mbox, UINT32 block_size, UINT32 rxmsg_size, void *pResetCb)
additional initialisation needed for mbox
INT32 m2mb_slave_sdio_recv_buflist_dequeue(INT32 instance_id, INT32 mbox, M2MB_SLAVE_SDIO_BUFFER_T **pbufinfo)
deques a list of completed receive buffers.
#define M2MB_SDIO_SLAVE_RECEIVE_BUFFER_COUNT
struct M2MB_OS_EV_HANDLE_TAG * M2MB_OS_EV_HANDLE
UINT8 tx_buffer[M2MB_SDIO_SLAVE_WRITE_BUFFER_MAX][2048]
M2MB_OS_SEM_HANDLE sem_handle
INT32 m2mb_slave_sdio_pre_init(UINT32 instance_id, INT32 mbox, UINT32 rx_buf_size, void *pInitCb, void *pSendCb, void *pRecvCb, void *pContext)
mobox initialisation
#define M2MB_SDIO_SLAVE_WRITE_BUFFER_MAX
struct M2M_SLAVE_SDIO_BUFFER_S M2MB_SLAVE_SDIO_BUFFER_T
void m2mb_slave_sdio_resume_recv(INT32 instance_id, INT32 mbox)
sends rx resume indication to host
INT32 m2mb_slave_sdio_send_buflist_dequeue(INT32 instance_id, INT32 mbox, M2MB_SLAVE_SDIO_BUFFER_T **pbufinfo)
deques a list of completed send buffers.
M2MB_SLAVE_SDIO_BUFFER_T rx_buf_info[M2MB_SDIO_SLAVE_RECEIVE_BUFFER_COUNT]
void m2mb_slave_sdio_pause_recv(INT32 instance_id, INT32 mbox)
sends rx pause indication to host
struct M2MB_SLAVE_SDIO_WRITE_REQUEST_S M2MB_SLAVE_SDIO_WRITE_REQUEST_T
M2MB_SLAVE_SDIO_WRITE_REQUEST_T write_req
struct M2M_SLAVE_SDIO_BUFFER_S * next
struct M2MB_SLAVE_SDIO_S M2MB_SLAVE_SDIO_T
INT32 m2m_slave_sdio_is_initialized(void)
mobox initialisation
void m2mb_slave_sdio_tx_credit_inc(INT32 instance_id, INT32 mbox)
Increments the Host Tx credit counter registers.
INT32 m2mb_slave_sdio_send_buflist_enqueue(INT32 instance_id, INT32 mbox, M2MB_SLAVE_SDIO_BUFFER_T *bufinfo)
enques tx buffer.
INT32 m2mb_slave_sdio_recv_buflist_enqueue(INT32 instance_id, INT32 mbox, M2MB_SLAVE_SDIO_BUFFER_T *bufinfo)
enques recieve buffer.