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US7057960B1 — Method and architecture for reducing the power consumption for memory devices in refresh operations
Priority Date: 2002-03-04, Publication Date: 2006-06-06, Current Assignee: Innomemory LLCReport Generated: 2022-07-26

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EP1256957A20.886System and method for performing partial array self-refresh operation in a semiconductor memory device.GRANT2002-11-132001-05-0726965544GreatSamsung Electronics Co LtdSamsung Electronics Co Ltd
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EP1125300A10.870METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICESGRANT2001-08-221998-10-2722666033GreatMonolithic System Technology IncMosys Inc
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EP1214713A10.860ARCHITECTURE  METHOD(S) AND CIRCUITRY FOR LOW POWER MEMORIESGRANT2002-06-191999-09-1723576591GreatCypress Semiconductor CorpCypress Semiconductor Corp
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US5291198A0.330Averaging flash analog-to-digital converterGRANT1994-03-011992-03-1610712246GoodElectronics Res and Service Org, Industrial Technology Research Institute ITRI, David Sarnoff Research Center IncElectronics Res and Service Org, Industrial Technology Research Institute ITRI, Sarnoff Corp
US5485625A0.314Method and apparatus for monitoring external events during a microprocessor's sleep modeGRANT1996-01-161992-06-2925422058GoodFord Motor CoVisteon Global Technologies Inc
US6885605B20.307Power-up signal generator for semiconductor memory devicesGRANT2005-04-262001-12-2119717371GoodHynix Semiconductor IncSK Hynix Inc
US6925024B20.307Zero power chip standby modeGRANT2005-08-022001-08-3025478789GoodMicron Technology IncRound Rock Research LLC
US20020007476A10.295STORAGEAPPLICATION2002-01-171997-09-2917388953GoodNEC CorpNEC Corp
US6518813B10.272Clock generating circuit and semiconductor integrated circuit using the sameGRANT2003-02-111999-01-2912106602GoodSeiko Epson CorpSeiko Epson Corp
EP1293985A10.256DATA BACKUP DEVICE AND STEP-UP/STEP-DOWN POWER SUPPLYGRANT2003-03-192000-06-0811736130GoodMitsubishi Electric CorpMitsubishi Electric Corp
US5748968A0.253Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requestsGRANT1998-05-051996-01-0524332921GoodCirrus Logic IncNvidia Corp
US20050198460A10.247System and method for managing memory compression transparent to an operating systemAPPLICATION2005-09-082001-02-1325126224GoodInternational Business Machines CorpMeta Platforms Inc
US6105138A0.231Method and apparatus for controlling electric source in information processing systemGRANT2000-08-151996-01-3111870688GoodHitachi Ltd, Hitachi Chubu Software Ltd, Hitachi Asahi Electronics Co LtdHitachi Ltd, Hitachi Chubu Software Ltd, Hitachi Asahi Electronics Co Ltd
US6324651B20.220Method and apparatus for saving device state while a computer system is in sleep modeGRANT2001-11-271998-11-1222701848GoodInternational Business Machines CorpLenovo PC International Ltd
KR100255259B1NRCIRCUITS  SYSTEMS AND METHODS FOR INTERFACING PROCESSING CIRCUITRY WITH A MEMORYGRANT2000-05-011995-11-0224204329Good
JPS6427094ANRMOS-TYPE SEMICONDUCTOR MEMORYGRANT1989-01-301987-07-2316168394Good
JPS5987695ANRSEMICONDUCTOR MEMORY DEVICEGRANT1984-05-211982-11-1116386998Good
JPS59167898ANRMEMORY CIRCUITGRANT1984-09-211983-03-1412614888Good
JPS5727491ANRREFRESH CONTROLLERGRANT1982-02-131980-07-2414303261Good
JPS55105893ANRDRIVING UNIT OF DYNAMIC MEMORYGRANT1980-08-131979-01-3111770423Good
JPH10255468ANRREFRESH DEVICE FOR DRAMGRANT1998-09-251997-03-1213060928Good
JPH09128965ANRSEMICONDUCTOR MEMORYGRANT1997-05-161995-10-2717923356Good
JPH07220469ANRSEMICONDUCTOR MEMORY DEVICEGRANT1995-08-181994-02-0412374332Good
JPH03149867ANRSEMICONDUCTOR INTEGRATED CIRCUITGRANT1991-06-261989-11-0717739011Good
GB2375865ANRCell data protection whilst refreshing memoryGRANT2002-11-272001-05-2519709970GoodHynix Semiconductor IncSK Hynix Inc
CN1195173ANRFlexible fuse placement in redundant semiconductor memoryGRANT1998-10-071997-03-2825243679Good
CN101038785ANRA high speed dram architecture with uniform access latencyGRANT2007-09-192000-07-074166723Good
US6055289A0.657Shared counterGRANT2000-04-251996-01-3024374934FairMicron Technology IncMicron Technology Inc
US6352868B10.562Method and apparatus for wafer level burn-inGRANT2002-03-052000-01-1921658531FairAdvanced Chip Engineering Technology IncAdvanced Chip Engineering Technology Inc
US7113208B10.439Image processing apparatus  image processing method and recording mediumGRANT2006-09-261998-02-2437018924FairCanon IncCanon Inc
US5530392A0.302Bus driver/receiver circuitry and systems and methods using the sameGRANT1996-06-251995-04-1123665236FairCirrus Logic IncIntellectual Ventures II LLC
US6306721B10.174Method of forming salicided poly to metal capacitorGRANT2001-10-232001-03-1625200138FairChartered Semiconductor Manufacturing Pte LtdGlobalFoundries Singapore Pte Ltd
US6949963B20.162Line driver with current source output and high immunity to RF signalsGRANT2005-09-272001-03-128179994FairKoninklijke Philips Electronics NVFuture Link Systems LLC
US20010008438A10.157Pixel array for LC silicon light valve featuring pixels with overlapping edgesAPPLICATION2001-07-191999-03-2923074484Fair
US8936573B20.152Infusion pump having missed bolus alarmGRANT2015-01-202002-02-2827753923FairSmiths Medical ASD IncSmiths Medical ASD Inc
US20030105092A10.047Prevention of loss and restoration of bone mass by certain prostaglandin agonistsAPPLICATION2003-06-051996-12-2021870485Fair
US5643533A0.027Method of packaged goods sterilizationGRANT1997-07-011995-05-1223746049Fair
US20050226820A10.023Non-crystalline saliva-soluble coatings for elastomeric monofilament dental tapesAPPLICATION2005-10-132001-01-2223000868FairWhiteHill Oral Technologies IncWhiteHill Oral Technologies Inc
US5338282A0.010Automatic trimming machineGRANT1994-08-161993-03-2321882822Fair
US1158364ANRPROCESS OF MAKING COHERING MASSES.GRANT1915-10-261915-03-103226414FairCONTINENTAL PROCESS CORPCONTINENTAL PROCESS Corp
US1008373ANRRUNNING-GEAR FOR VEHICLES.GRANT1911-11-141908-02-103076684FairWILLIAM D ELLWANGERWILLIAM D ELLWANGER
JPH0982088ANRCOMPUTER SYSTEMGRANT1997-03-281995-09-1817032193Fair
JPH0773682ANRSEMICONDUCTOR MEMORYGRANT1995-03-171993-06-1215829018Fair
JPH07220470ANRMETHOD AND APPARATUS FOR CONTROLLING REFRESHING OPERATION TO MEMORYGRANT1995-08-181994-01-2711664945Fair
JPH06103758ANRDYNAMIC TYPE SEMICONDUCTOR STORAGE DEVICEGRANT1994-04-151992-09-2117219588Fair
JPH056669ANRMOS TYPE RAMGRANT1993-01-141991-11-1117803947Fair
JPH0422887ANRMETHOD FOR CHECKING SEMICONDUCTOR MEMORY CIRCUITGRANT1992-01-271990-05-1614957732Fair
JPH03272088ANRSEMICONDUCTOR STORAGE DEVICEGRANT1991-12-031990-03-2013438249Fair
JPH02192096ANRSELECTIVE REFRESH CONTROLLERGRANT1990-07-271989-01-2011735305Fair
JPH01298596ANRSEMICONDUCTOR MEMORYGRANT1989-12-011988-05-2615048301Fair
JP2002132577ANRDATA PROCESSING SYSTEMAPPLICATION2002-05-101993-10-1527334691Fair
JP2001043677ANRSEMICONDUCTOR MEMORYAPPLICATION2001-02-161999-08-0316735302Fair

Predictive Analytics

Composite Research Score (1-10)
9
  HARD
Art VolumeMEDIUM
Tech ComplexityINTRICATE
Priority DateEARLY
Tech DiversityBROAD
Expert Services Estimate$4,950 — $5,400
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There is where a graph would go if the browser supported it.

CPC Technology Profile

Possible Classes
1,405
Recommended Classes
352
Government Assigned Classes
1
CPC
Title
Score
G11C11/406Management or control of the refreshing or charge-regeneration cycles2.284
G11C11/40618Refresh operations over multiple banks or interleaving1.947
G11C11/40611External triggering or timing of internal or partially internal refresh operations  e.g. auto-refresh or CAS-before-RAS triggered refresh1.752
G11C11/4085Word line control circuits  e.g. word line drivers  - boosters  - pull-up  - pull-down  - precharge1.748
G11C8/10Decoders1.704
G11C11/40615Internal triggering or timing of refresh  e.g. hidden refresh  self refresh  pseudo-SRAMs1.693
G11C29/76using address translation or modifications1.676
G11C29/4401for self repair1.676
G11C7/1006Data managing  e.g. manipulating data before writing or reading out  data bus switches or control circuits therefor1.644
G11C11/2275Writing or programming circuits or methods1.629
G06F13/1668Details of memory controller1.609
G11C16/102External programming circuits  e.g. EPROM programmers| In-circuit programming or reprogramming| EPROM emulators1.540
G11C13/0026Bit-line or column circuits1.540
G06F13/4234being a memory bus1.537
G06F13/1673using buffers1.537
G11C11/4074Power supply or voltage generation circuits  e.g. bias voltage generators  substrate voltage generators  back-up power  power control circuits1.508
G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device | geometrical lay-out of the components in integrated circuits  | (ref: H01L27/0207)1.508
H01L27/2409comprising two-terminal selection components  e.g. diodes1.508
G06F11/1068in sector programmable memories  e.g. flash disk | (ref: G06F11/1072)|  takes precedence1.486
G06F11/1004to protect a block of data words  e.g. CRC or checksum | (ref: G06F11/1076)|  takes precedence| security arrangements for protecting computers or computer systems against unauthorized activity | (ref: G06F21/00)1.486
G11C11/44using super-conductive elements  e.g. cryotron1.474
G06F3/0659Command handling arrangements  e.g. command buffers  queues  command scheduling1.470
G11C11/4091Sense or sense/refresh amplifiers  or associated sense circuitry  e.g. for coupled bit-line precharging  equalising or isolating1.470
G11C8/16Multiple access memory array  e.g. addressing one storage element via at least two independent addressing line groups1.465
G11C11/4097Bit-line organisation  e.g. bit-line layout  folded bit lines1.465
G11C7/18Bit line organisation| Bit line lay-out1.465
G06F3/0619in relation to data integrity  e.g. data losses  bit errors1.458
G06F1/3275Power saving in memory  e.g. RAM  cache1.456
G06F1/3225of memory devices1.456
G06F11/076by exceeding a count or rate limit  e.g. word- or bit count limit1.446
G06F12/0284Multiple user address space allocation  e.g. using different base addresses | interprocessor communication | (ref: G06F15/163)1.421
G06F11/073in a memory management context  e.g. virtual memory or cache management | memory management | (ref: G06F12/00)| | testing of static memory units | (ref: G11C29/00)1.415
G11C11/2277Verifying circuits or methods1.415
G06F11/1044with specific ECC/EDC distribution1.406
G06F11/1052Bypassing or disabling error detection or correction1.406
G11C29/42using error correcting codes [ECC] or parity check1.405
G11C7/1009Data masking during input/output1.405
G11C29/52Protection of memory contents| Detection of errors in memory contents1.405
G11C11/419Read-write [R-W] circuits1.402
G11C7/1075for multiport memories each having random access ports and serial ports  e.g. video RAM1.402
G06F9/3855Reordering  e.g. using a queue  age tags1.396
G11C29/24Accessing extra cells  e.g. dummy cells or redundant cells1.392
G11C29/10Test algorithms  e.g. memory scan [MScan] algorithms| Test patterns  e.g. checkerboard patterns 1.392
G11C15/04using semiconductor elements1.392
G06F11/0727in a storage system  e.g. in a DASD or network based storage system | drivers for digital recording or reproducing units | (ref: G06F3/06)| | circuits for error detection or correction within digital recording or reproducing units | (ref: G11B20/18)| | for distributed storage of data in networks  e.g. transport arrangements for network file system [NFS]  storage area networks [SAN] or network attached storage [NAS]  | (ref: H04L67/1097)1.390
G06F11/1469Backup restoration techniques1.390
G11C16/08Address circuits| Decoders| Word-line control circuits1.388
G06F3/0611in relation to response time1.388
G11C16/10Programming or data input circuits1.388
G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written1.384
G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells1.384
G06F3/0688Non-volatile semiconductor memory arrays1.381
G06F11/1012using codes or arrangements adapted for a specific type of error | (ref: G06F11/1048)|  takes precedence1.380
G11C7/1057Data output buffers  e.g. comprising level conversion circuits  circuits for adapting load1.367
G11C11/4072Circuits for initialization  powering up or down  clearing memory or presetting1.367
G06F12/0238Memory management in non-volatile memory  e.g. resistive RAM or ferroelectric memory1.356
G06F12/063for I/O modules  e.g. memory mapped I/O | I/O protocol | (ref: G06F13/42)1.356
G06F12/1408by using cryptography | for digital transmission | (ref: H04L9/00)1.356
G11C16/12Programming voltage switching circuits1.355
H02M3/07using capacitors charged and discharged alternately by semiconductor devices with control electrode |   e.g. charge pumps1.353
G11C5/145Applications of charge pumps| Boosted voltage circuits| Clamp circuits therefor | (ref: G11C5/141)|  takes precedence1.353
G11C11/412using field-effect transistors only1.350
H03K19/1776for memories1.346
H03K5/1565the output pulses having a constant duty cycle1.336
G11C7/22Read-write [R-W] timing or clocking circuits| Read-write [R-W] control signal generators or management 1.336
G11C11/4076Timing circuits | for regeneration management | (ref: G11C11/406)1.336
G11C7/10Input/output [I/O] data interface arrangements  e.g. I/O data control circuits  I/O data buffers1.336
B41J2/04536using history data1.336
B41J2/04541Specific driving circuit1.336
G06F13/382using universal interface adapter1.323
G11C7/222Clock generating  synchronizing or distributing circuits within memory device1.323
G11C13/004Reading or sensing circuits or methods1.319
G11C29/022in I/O circuitry1.319
G06F3/0632by initialisation or re-initialisation of storage systems1.319
G06F13/4243with synchronous protocol1.308
G11C7/1072for memories with random access ports synchronised on clock signal pulse trains  e.g. synchronous memories  self timed memories1.308
G06N3/0635using analogue means1.307
G11C11/2273Reading or sensing circuits or methods1.304
G11C5/148Details of power up or power down circuits  standby circuits or recovery circuits1.304
G06F11/1076Parity data used in redundant arrays of independent storages  e.g. in RAID systems1.292
G11C5/02Disposition of storage elements  e.g. in the form of a matrix array1.292
G06F13/1678using bus width1.292
G11C29/18Address generation devices| Devices for accessing memories  e.g. details of addressing circuits1.290
G11C7/20Memory cell initialisation circuits  e.g. when powering up or down  memory clear  latent image memory1.289
G11C16/0483comprising cells having several storage transistors connected in series1.289
G11C11/4093Input/output [I/O] data interface arrangements  e.g. data buffers1.289
B41J2/0455Details of switching sections of circuit  e.g. transistors1.288
B41J2/0452reducing demand in current or voltage1.288
G11C13/0069Writing or programming circuits or methods1.287
G11C7/1084Data input buffers  e.g. comprising level conversion circuits  circuits for adapting load1.284
G11C7/1048Data bus control circuits  e.g. precharging  presetting  equalising1.284
G06F21/62Protecting access to data via a platform  e.g. using keys or access control rules1.284
G06F3/0622in relation to access1.284
G06F9/30036Instructions to perform operations on packed data  e.g. vector operations1.278
G06F9/3012Organisation of register space  e.g. banked or distributed register file1.278
G06F3/0625Power saving in storage systems1.276
G11C11/5642Sensing or reading circuits| Data output circuits1.271
G06F3/0655Vertical data movement  i.e. input-output transfer| data movement between one or more hosts and one or more storage devices1.271
G06F1/3234Power saving characterised by the action undertaken1.267
G11C8/20Address safety or protection circuits  i.e. arrangements for preventing unauthorized or accidental access1.266
G06F3/0679Non-volatile semiconductor memory device  e.g. flash memory  one time programmable memory [OTP]1.266
G11C8/04using a sequential addressing device  e.g. shift register  counter1.259
G06F12/0207with multidimensional access  e.g. row/column  matrix1.259
G06F11/1048using arrangements adapted for a specific error detection or correction feature1.257
G11C7/1078Data input circuits  e.g. write amplifiers  data input buffers  data input registers  data input level conversion circuits1.254
G11C29/36Data generation devices  e.g. data inverters1.246
G11C29/028with adaption or trimming of parameters1.246
G11C13/0035Evaluating degradation  retention or wearout  e.g. by counting writing cycles1.243
H04B14/023using pulse amplitude modulation1.242
G06F1/08Clock generators with changeable or programmable clock frequency1.241
G06F3/0637Permissions1.237
G06F12/1466Key-lock mechanism1.237
G11C11/40603Arbitration  priority and concurrent access to memory cells for read/write or refresh operations1.235
G11C11/4078Safety or protection circuits  e.g. for preventing inadvertent or unauthorised reading or writing| Status cells| Test cells | protection of memory contents during checking or testing | (ref: G11C29/52)1.233
G11C13/003Cell access1.231
G11C13/0033Disturbance prevention or evaluation| Refreshing of disturbed memory data1.231
G11C7/12Bit line control circuits  e.g. drivers  boosters  pull-up circuits  pull-down circuits  precharging circuits  equalising circuits  for bit lines1.231
G06F11/1016Error in accessing a memory location  i.e. addressing error1.230
G11C5/147Voltage reference generators  voltage or current regulators| Internally lowered supply levels| Compensation for voltage drops | (ref: G11C5/141)|  takes precedence1.230
G11C5/04Supports for storage elements |   e.g. memory modules| Mounting or fixing of storage elements on such supports1.228
G11C16/0425comprising cells containing a merged floating gate and select transistor1.226
G11C11/1659Cell access1.226
G11C11/1675Writing or programming circuits or methods1.226
G11C16/349Arrangements for evaluating degradation  retention or wearout  e.g. by counting erase cycles1.225
G11C16/26Sensing or reading circuits| Data output circuits1.225
H04L1/0032Without explicit signalling1.220
G11C7/1051Data output circuits  e.g. read-out amplifiers  data output buffers  data output registers  data output level conversion circuits1.220
H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for |   e.g. in combination with batteries | (ref: H01L23/49593)|   | (ref: H01L23/49596)|  take precedence1.217
H01L25/16the devices being of types provided for in two or more different main groups of | (ref: H01L27/00)|  - | (ref: H01L49/00)|  | and | (ref: H01L51/00)|   e.g. forming hybrid circuits | interconnections for hybrid circuits | (ref: H01L23/5389)1.217
H01L35/28operating with Peltier or Seebeck effect only1.217
H01L29/7889Vertical transistors  i.e. transistors having source and drain not in the same horizontal plane1.216
H01L27/10802comprising floating-body transistors  e.g. floating-body cells1.216
G11C11/4096Input/output [I/O] data management or control circuits  e.g. reading or writing circuits  I/O drivers or bit-line switches 1.216
G11C13/0004comprising amorphous/crystalline phase transition cells1.216
H03K19/17744for input/output signals1.208
H03K19/17756for partial configuration or partial reconfiguration1.208
G06F11/1024Identification of the type of error1.207
G06F12/0646Configuration or reconfiguration1.206
G11C11/221using ferroelectric capacitors1.206
G11C11/40626Temperature related aspects of refresh operations1.206
G11C7/1045Read-write mode select circuits1.206
G06F1/206comprising thermal management1.203
G06F13/1652in a multiprocessor architecture | interprocessor communication using common memory | (ref: G06F15/167)1.202
B41J2/14153Structures including a sensor1.201
H01L27/11Static random access memory structures1.199
G06F11/106Correcting systematically all correctable errors  i.e. scrubbing1.196
G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells1.193
G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines  e.g. word-line  bit-line  cross-over resistance  propagation delay1.185
H01L27/10897Peripheral structures1.185
H04L25/03057with a recursive structure | (ref: H04L25/03031)|  takes precedence1.184
H04L25/03878Line equalisers| line build-out devices1.184
H04L25/03146with a recursive structure | (ref: H04L25/03127)|  takes precedence1.184
G06F13/1689Synchronisation and timing concerns | synchronisation on a memory bus | (ref: G06F13/4234)1.184
G11C11/5692read-only digital stores using storage elements with more than two stable states1.182
G11C7/1039using pipelining techniques  i.e. using latches between functional memory parts  e.g. row/column decoders  I/O buffers  sense amplifiers1.181
G11C16/3481Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress  e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming1.178
G11C11/5628Programming or writing circuits| Data input circuits1.178
G09G3/30using electroluminescent panels1.170
G06F3/0658Controller construction arrangements1.163
G06F1/26Power supply means  e.g. regulation thereof | for memories | (ref: G11C)1.161
H01L25/18the devices being of types provided for in two or more different subgroups of the same main group of groups | (ref: H01L27/00)|  - | (ref: H01L51/00)|  | comprising devices provided for in | (ref: H01L27/144)|  and subgroups  | see|  | (ref: H01L27/144)|  and subgroups1.158
H03K19/018507Interface arrangements1.158
H03K19/00361in field effect transistor circuits1.158
G11C11/402with charge regeneration individual to each memory cell  i.e. internal refresh1.152
G06F3/061Improving I/O performance1.150
H01L27/11531Simultaneous manufacturing of periphery and memory cells1.142
G06N3/0445Feedback networks  e.g. hopfield nets  associative networks1.142
G06F12/1416by checking the object accessibility  e.g. type of access defined by the memory independently of subject rights | (ref: G06F12/1458)|  takes precedence1.142
G06F12/1027using associative or pseudo-associative address translation means  e.g. translation look-aside buffer [TLB]1.142
G06F12/1475in a virtual system  e.g. with translation means1.142
G11C29/08Functional testing  e.g. testing during refresh  power-on self testing [POST] or distributed testing1.142
G11C7/227Timing of memory operations based on dummy memory elements or replica circuits1.142
G06F21/78to assure secure storage of data | address-based protection against unauthorised use of memory | (ref: G06F12/14)| | record carriers for use with machines and with at least a part designed to carry digital markings | (ref: G06K19/00)1.138
G11C7/24Memory cell safety or protection circuits  e.g. arrangements for preventing inadvertent reading or writing| Status cells| Test cells1.138
G11C11/54using elements simulating biological cells  e.g. neuron1.133
G11C11/401forming cells needing refreshing or charge regeneration  i.e. dynamic cells1.125
G06F3/065Replication mechanisms1.123
G06F30/30Circuit design1.123
H04L9/3278using physically unclonable functions [PUF]1.123
G11C16/22Safety or protection circuits preventing unauthorised or accidental access to memory cells1.123
G06F21/72in cryptographic circuits1.123
G06F13/4072Drivers or receivers | (ref: G06F13/4086)|  takes precedence| for multistate logic circuits | (ref: H03K19/0002)1.122
G06F12/16Protection against loss of memory contents | contains no material  | see|  | (ref: G06F11/00)1.121
G11C29/02Detection or location of defective auxiliary circuits  e.g. defective refresh counters1.119
G11C7/04with means for avoiding disturbances due to temperature effects1.118
G06F3/0653Monitoring storage devices or systems1.118
G06F13/1636using refresh1.117
G11C11/2257Word-line or row circuits1.116
B41J2/17546electronically1.114
B41J2/17566Ink level or ink residue control1.114
B41J2/04581controlling heads based on piezoelectric elements1.112
B41J2/04543Block driving1.112
G06F21/44Program or device authentication1.111
G06F21/608Secure printing1.111
H05B45/10Controlling the intensity of the light1.109
G09G3/20for presentation of an assembly of a number of characters  e.g. a page  by composing the assembly by combination of individual elements arranged in a matrix | no fixed position being assigned to or needed to be assigned to the individual characters or partial characters1.109
B60Q1/143combined with another condition  e.g. using vehicle recognition from camera images or activation of wipers1.109
H03K5/135by the use of time reference signals  e.g. clock signals1.108
H03K3/012Modifications of generator to improve response time or to decrease power consumption1.108
G11C11/40622Partial refresh of memory arrays1.106
G11C29/56External testing equipment for static stores  e.g. automatic test equipment [ATE]| Interfaces therefor1.106
G06F12/0246in block erasable memory  e.g. flash memory1.103
G06F3/0631by allocating resources to storage systems1.103
G09G3/3225using an active matrix1.102
G09G3/32semiconductive  e.g. using light-emitting diodes [LED]1.102
G11C29/50004of threshold voltage1.102
H03M13/05using block codes  i.e. a predetermined number of check bits joined to a predetermined number of information bits | (ref: H03M13/2906)|  takes precedence1.099
C03C3/321Chalcogenide glasses  e.g. containing S  Se  Te1.099
H01L45/142Sulfides  e.g. CuS1.099
G11C7/1087Data input latches1.099
G11C8/08Word line control circuits  e.g. drivers  boosters  pull-up circuits  pull-down circuits  precharging circuits  for word lines1.098
G06F13/1684using multiple buses1.097
G06F9/44505Configuring for program initiating  e.g. using registry  configuration files1.092
H03K19/17748Structural details of configuration resources1.092
G06F3/067Distributed or networked storage systems  e.g. storage area networks [SAN]  network attached storage [NAS]1.089
G06F3/062Securing storage systems1.089
H04L67/1097for distributed storage of data in networks  e.g. transport arrangements for network file system [NFS]  storage area networks [SAN] or network attached storage [NAS]1.089
G06N3/063using electronic means1.087
H03M1/14Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit1.085
H03M1/144the steps being performed sequentially in a single stage  i.e. recirculation type | (ref: H03M1/141)|   | (ref: H03M1/143)|   | (ref: H03M1/16)|  take precedence1.085
G11C29/50016of retention1.085
G11C11/407for memory cells of the field-effect type1.084
G11C7/00Arrangements for writing information into  or reading information out from  a digital store | (ref: G11C5/00)|  takes precedence| auxiliary circuits for stores using semiconductor devices | (ref: G11C11/4063)|   | (ref: G11C11/413)1.080
G06F3/0656Data buffering arrangements1.079
G06F3/0607by facilitating the process of upgrading existing storage systems  e.g. for improving compatibility between host and storage device1.079
A47G9/109adapted to lie on the side and in supine position1.077
G06F3/064Management of blocks1.076
G06F3/0604Improving or facilitating administration  e.g. storage management1.076
B41J2/0458controlling heads based on heating elements forming bubbles1.076
G06F12/0607Interleaved addressing1.076
G06F12/0623for memory modules1.076
G11C16/34Determination of programming status  e.g. threshold voltage  overprogramming or underprogramming  retention1.070
G06F13/28using burst mode transfer  e.g. direct memory access | DMA|   cycle steal | (ref: G06F13/32)|  takes precedence1.070
H01L27/11512characterised by the boundary region between the core and peripheral circuit regions1.069
H01L23/5226Via connections in a multilevel interconnection structure1.069
H01L27/2427of the Ovonic threshold switching type1.069
G09G3/2092Details of a display terminals using a flat panel  the details relating to the control arrangement of the display terminal and to the interfaces thereto | suitable for both CRT and flat panel | (ref: G09G5/003)| | specific for a CRT | (ref: G09G1/165)1.068
G09G3/22using controlled light sources1.068
G11C16/32Timing circuits1.067
G06F3/0613in relation to throughput1.067
H01L23/481Internal lead connections  e.g. via connections  feedthrough structures1.066
H01L25/0657Stacked arrangements of devices1.066
G11C11/40using transistors1.066
H03K19/17724Structural details of logic blocks1.062
G11C11/005comprising combined but independently operative RAM-ROM  RAM-PROM  RAM-EPROM cells1.061
G06F16/2237Vectors  bitmaps or matrices1.058
H03M7/3082Vector coding | for television signals  | see|  | (ref: H04N19/94)1.058
G06F15/7821Tightly coupled to memory  e.g. computational memory  smart memory  processor in memory1.056
G11C8/18Address timing or clocking circuits| Address control signal generation or management  e.g. for row address strobe [RAS] or column address strobe [CAS] signals1.056
H04N5/3696SSIS architecture characterized by non-identical  non-equidistant or non-planar pixel layout  sensor embedding other types of pixels not meant for producing an image signal  e.g. fovea sensors or display pixels | Imager structures | (ref: H01L27/146)1.056
H04N5/2357Detection of flicker frequency or flicker suppression  e.g. due to fluorescent tube illumination1.056
H04N5/3535with different integration times within the sensor1.056
H04N5/2353by influencing the exposure time  e.g. shutter | (ref: H04N5/2352)|  takes precedence| within the image sensor | (ref: H04N5/353)1.056
H04N5/37452comprising additional storage means | by controlling the amount of charges storable in the pixel | (ref: H04N5/3559)1.056
G11C11/225Auxiliary circuits1.055
G11C11/2259Cell access1.055
G11C14/0072and the nonvolatile element is a ferroelectric element1.055
G06F11/1008in individual solid state devices | (ref: G06F11/1004)|  takes precedence1.054
G11C8/00Arrangements for selecting an address in a digital store | for stores using transistors | (ref: G11C11/407)|   | (ref: G11C11/413)1.054
G09G5/399using two or more bit-mapped memories  the operations of which are switched in time  e.g. ping-pong buffers1.047
G09G3/2014by modulation of the duration of a single pulse during which the logic level remains constant1.047
G06F11/08Error detection or correction by redundancy in data representation  e.g. by using checking codes1.045
G06F3/0641De-duplication techniques1.045
G11C11/22using ferroelectric elements1.044
G11C11/14using thin-film elements1.044
H03L7/0807concerning mainly a recovery circuit for the reference signal1.043
H03L7/085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal | (ref: H03L7/10)|  takes precedence| frequency or phase detection comparison in general | (ref: H03D3/00)|   | (ref: H03D13/00)1.043
H04L7/0338the correction of the phase error being performed by a feed forward loop1.043
G11C13/0019comprising bio-molecules1.042
G01N27/3278involving nanosized elements  e.g. nanogaps or nanoparticles | nanopores | (ref: G01N33/48721)| | magnetic beads | (ref: G01N27/745)1.042
G11C29/48Arrangements in static stores specially adapted for testing by means external to the store  e.g. using direct memory access [DMA] or using auxiliary access paths1.040
G11C29/12Built-in arrangements for testing  e.g. built-in self testing [BIST] | or interconnection details1.040
G11C29/56008Error analysis  representation of errors1.040
G11C11/4023using field effect transistors1.039
G06F13/16for access to memory bus | (ref: G06F13/28)|  takes precedence1.038
G01S7/4815using multiple transmitters1.035
G01S17/8943D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels  e.g. time-of-flight cameras or flash lidar1.035
G01S17/89for mapping or imaging1.035
G11C11/4087Address decoders  e.g. bit - or word line decoders| Multiple line decoders1.035
H02P27/08with pulse width modulation1.033
B60L15/20for control of the vehicle or its driving motor to achieve a desired performance  e.g. speed  torque  programmed variation of speed1.033
B60L3/0023Detecting  eliminating  remedying or compensating for drive train abnormalities  e.g. failures within the drive train1.033
G06F13/4295using an embedded synchronisation1.033
H04L63/0428wherein the data content is protected  e.g. by encrypting or encapsulating the payload1.026
H04L9/3252using DSA or related signature schemes  e.g. elliptic based signatures  ElGamal or Schnorr schemes1.026
G06F21/575Secure boot1.025
H04L9/3249using RSA or related signature schemes  e.g. Rabin scheme1.025
G06F11/0757by exceeding a time limit  i.e. time-out  e.g. watchdogs1.025
G06F21/123by using dedicated hardware  e.g. dongles  smart cards  cryptographic processors  global positioning systems [GPS] devices1.025
H01L27/2454of the vertical channel field-effect transistor type1.025
H01L27/1157with cell select transistors  e.g. NAND1.025
H01L27/11568characterised by the memory core region | three-dimensional arrangements | (ref: H01L27/11578)1.025
G06F3/0608Saving storage space on storage systems1.024
G06F3/0616in relation to life time  e.g. increasing Mean Time Between Failures [MTBF]1.024
G11C7/106Data output latches1.024
H03M13/1108Hard decision decoding  e.g. bit flipping  modified or weighted bit flipping1.022
G01S7/4868Controlling received signal intensity or exposure of sensor1.020
G01S7/4863Detector arrays  e.g. charge-transfer gates1.020
G01R31/318513Test of Multi-Chip-Moduls1.020
G01R31/2853Electrical testing of internal connections or -isolation  e.g. latch-up or chip-to-lead connections | (ref: G01R31/31717)|  takes precedence| test of chip-to-PCB or lead-to-PCB connections | (ref: G01R31/66)1.020
H01L22/14for electrical parameters  e.g. resistance  deep-levels  CV  diffusions by electrical means1.020
G11C16/105Circuits or methods for updating contents of nonvolatile memory  especially with 'security' features to ensure reliable replacement  i.e. preventing that old data is lost before new data is reliably written1.019
G11C17/18Auxiliary circuits  e.g. for writing into memory1.017
G06F13/4027using bus bridges | (ref: G06F13/4022)|  takes precedence1.017
G06F15/7867with reconfigurable architecture1.017
G11C11/409Read-write [R-W] circuits 1.017
H04N5/32Transforming X-rays | image transformers | (ref: H01J31/00)1.016
H04N5/378Readout circuits  e.g. correlated double sampling [CDS] circuits  output amplifiers or A/D converters1.016
G11C7/1042using interleaving techniques  i.e. read-write of one part of the memory while preparing another part1.016
G11C8/06Address interface arrangements  e.g. address buffers1.015
H01L27/11582the channels comprising vertical portions  e.g. U-shaped channels1.015
H01L45/143Selenides  e.g. GeSe1.015
H01L27/249the switching components being connected to a common vertical conductor1.015
G11C5/06Arrangements for interconnecting storage elements electrically  e.g. by wiring1.012
G11C11/4063Auxiliary circuits  e.g. for addressing  decoding  driving  writing  sensing or timing1.012
H01L27/0694comprising components formed on opposite sides of a semiconductor substrate1.009
H01L27/115Electrically programmable read-only memories| Multistep manufacturing processes therefor1.009
G11C11/408Address circuits1.009
H04L27/2614Peak power aspects1.008
H03F3/211using a combination of several amplifiers | (ref: H03F3/60)|  takes precedence1.008
F21S41/675by moving reflectors1.007
B60Q1/1407General lighting circuits comprising dimming circuits1.007
G05F1/563including two stages of regulation at least one of which is output level responsive  e.g. coarse and fine regulation1.007
H02M1/088for the simultaneous control of series or parallel connected semiconductor devices1.007
H02M3/158including plural semiconductor devices as final control devices for a single load1.007
G11C11/4094Bit-line management or control circuits1.006
G11C7/06Sense amplifiers| Associated circuits |   e.g. timing or triggering circuits1.006
G11C29/20using counters or linear-feedback shift registers [LFSR]1.006
G11C11/403with charge regeneration common to a multiplicity of memory cells  i.e. external refresh1.005
G06F12/1441for a range1.004
G06F9/30021Compare instructions  e.g. Greater-Than  Equal-To  MINMAX1.004
G06F12/1483using an access-table  e.g. matrix or list1.004
G11C11/34using semiconductor devices1.004
G06F17/16Matrix or vector computation |   e.g. matrix-matrix or matrix-vector multiplication  matrix factorization | matrix transposition | (ref: G06F7/78)1.004
G11C8/14Word line organisation| Word line lay-out1.003
G11C29/806by reducing size of decoders1.003
G01R19/16533characterised by the application1.002
G06F21/755with measures against power attack1.002
H03K19/17796for physical disposition of blocks1.002
H05B45/50responsive to malfunctions or undesirable behaviour of LEDs| responsive to LED life| Protective circuits1.001
H01L29/40117the electrodes comprising a charge-trapping insulator0.999
H01L27/11565characterised by the top-view layout0.999
G06F13/4282on a serial bus  e.g. I2C bus  SPI bus | on daisy chain buses | (ref: G06F13/4247)0.998
G06F13/387for adaptation of different data processing systems to different peripheral devices  e.g. protocol converters for incompatible systems  open system0.998
H04N5/345by partially reading an SSIS array |   i.e. by outputting a number of pixels less than the number of pixels present on the image sensor0.997
H04N5/37455comprising A/D  V/T  V/F  I/T or I/F converters0.997
G06F21/64Protecting data integrity  e.g. using checksums  certificates or signatures0.997
G06F21/602Providing cryptographic facilities or services0.997
G11C5/14Power supply arrangements |   e.g. power down  chip selection or deselection  layout of wirings or power grids  or multiple supply levels0.997
G06F21/6227where protection concerns the structure of data  e.g. records  types  queries0.994
H01L23/49838Geometry or layout0.994
H01L23/552Protection against radiation  e.g. light | or electromagnetic waves0.994
G11C5/143Detection of memory cassette insertion or removal| Continuity checks of supply or ground lines| Detection of supply variations  interruptions or levels | (ref: G11C5/148)|  takes precedence| | Switching between alternative supplies | (ref: G11C5/141)|  takes precedence0.993
G01R27/2605Measuring capacitance | capacitive sensors | (ref: G01D5/24)0.993
G11C29/021in voltage or current generators0.993
G06F13/1694Configuration of memory controller to different memory types0.993
G11C11/418Address circuits0.990
G06F12/0223User address space allocation  e.g. contiguous or non contiguous base addressing0.989
G11C13/0016comprising polymers0.989
H03K21/403Arrangements for storing the counting state in case of power supply interruption0.986
H04L9/0618Block ciphers  i.e. encrypting groups of characters of a plain text message using fixed encryption transformation0.986
G06F21/55Detecting local intrusion or implementing counter-measures0.986
G11C29/026in sense amplifiers0.984
G11C7/02with means for avoiding parasitic signals0.984
G06T1/60Memory management0.983
G11C29/50008of impedance0.983
G11C13/0038Power supply circuits0.982
H03K17/06Modifications for ensuring a fully conducting state0.980
H03K17/28Modifications for introducing a time delay before switching | modifications to provide a choice of time-intervals for executing more than one switching action | (ref: H03K17/296)0.980
G11C7/1066Output synchronization0.979
G01S7/4865Time delay measurement  e.g. time-of-flight measurement  time of arrival measurement or determining the exact position of a peak | peak detection in noise  signal conditioning | (ref: G01S7/487)0.978
G11C16/14Circuits for erasing electrically  e.g. erase voltage switching circuits0.977
H04L12/12Arrangements for remote connection or disconnection of substations or of equipment thereof0.977
H04L41/0803Configuration setting0.977
G11C29/783with refresh of replacement cells  e.g. in DRAMs0.976
G11C11/40607Refresh operations in memory devices with an internal cache or data buffer0.975
H01L27/108Dynamic random access memory structures0.975
G06F12/02Addressing or allocation| Relocation | program address sequencing | (ref: G06F9/00)| | arrangements for selecting an address in a digital store | (ref: G11C8/00)0.973
G11C11/04using storage elements having cylindrical form  e.g. rod  wire | (ref: G11C11/12)|   | (ref: G11C11/14)|  take precedence0.973
B41J2/355Control circuits for heating-element selection0.972
B41J2/36Print density control0.972
G11C5/00Details of stores covered by group | (ref: G11C11/00)0.971
G01S17/10using transmission of interrupted  pulse-modulated waves | determination of distance by phase measurements | (ref: G01S17/32)0.971
G11C29/50Marginal testing  e.g. race  voltage or current testing0.971
G11C11/413Auxiliary circuits  e.g. for addressing  decoding  driving  writing  sensing  timing or power reduction0.971
G11C29/00Checking stores for correct operation | | Subsequent repair| Testing stores during standby or offline operation0.971
G06F12/00Accessing  addressing or allocating within memory systems or architectures | digital input from  or digital output to record carriers  e.g. to disk storage units  | (ref: G06F3/06)0.969
G11C29/14Implementation of control logic  e.g. test mode decoders0.969
G01R31/31701Arrangements for setting the Unit Under Test [UUT] in a test mode0.969
G09G3/3266Details of drivers for scan electrodes0.968
H01L27/2481arranged in a direction perpendicular to the substrate  e.g. 3D cell arrays  details of the vertical layout0.967
H01L23/3114the device being a chip scale package  e.g. CSP0.967
G11C14/0018whereby the nonvolatile element is an EEPROM element  e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor0.967
H03M7/70Type of the data to be coded  other than image and sound0.967
H04L25/4917using multilevel codes0.967
G06F13/385for adaptation of a particular data processing system to different peripheral devices0.967
H04L25/0272Arrangements for coupling to multiple lines  e.g. for differential transmission0.967
H04L9/06the encryption apparatus using shift registers or memories for block-wise | or stream|  coding  e.g. DES systems | or RC4| Hash functions| Pseudorandom sequence generators0.966
G01L1/144with associated circuitry | (ref: G01L1/146)|  and | (ref: G01L1/148)|  take precedence0.966
G01R31/3181Functional testing | (ref: G01R31/3177)|  takes precedence0.966
G01R27/02Measuring real or complex resistance  reactance  impedance  or other two-pole characteristics derived therefrom  e.g. time constant | by measuring phase angle only | (ref: G01R25/00)0.966
H03K21/38Starting  stopping or resetting the counter | counters with a base other than a power of two | (ref: H03K23/48)|   | (ref: H03K23/66)0.966
H01L29/402Field plates0.964
H01L27/11529of memory regions comprising cell select transistors  e.g. NAND0.964
H01L27/11556the channels comprising vertical portions  e.g. U-shaped channels0.964
G06T3/4023Decimation- or insertion-based scaling  e.g. pixel or line decimation0.964
F21S41/153arranged in a matrix0.964
H03M1/68with conversions of different sensitivity  i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits0.964
H03M1/462Details of the control circuitry  e.g. of the successive approximation register0.964
H01L27/10including a plurality of individual components in a repetitive configuration0.964
H03M1/66Digital/analogue converters | (ref: H03M1/001)|  â€“ |  | (ref: H03M1/10)|  take precedence0.964
H03M1/662Multiplexed conversion systems0.964
G11C7/08Control thereof0.964
G06F7/4806Computations with complex numbers0.963
H03L1/02against variations of temperature only0.961
H03L1/022by indirect stabilisation  i.e. by generating an electrical correction signal which is a function of the temperature | (ref: H03L1/021)|  takes precedence0.961
H03L7/0995the oscillator comprising a ring oscillator0.961
G06F12/0877Cache access modes0.960
G06F12/0815Cache consistency protocols0.960
B41J2/04573Timing| Delays0.960
G09G3/3208organic  e.g. using organic light-emitting diodes [OLED]0.960
G11C16/04using variable threshold transistors  e.g. FAMOS0.959
G11C11/405with three charge-transfer gates  e.g. MOS transistors  per cell0.959
G06F13/161with latency improvement0.959
G09G3/36using liquid crystals0.959
H04N5/3577for reducing electromagnetic interferences  e.g. EMI reduction  clocking noise0.959
G06V40/1318using electro-optical elements or layers  e.g. electroluminescent sensing0.959
H01L27/1052Memory structures and multistep manufacturing processes therefor not provided for in groups | (ref: H01L27/1055)|  - | (ref: H01L27/112)0.958
H01L29/78642Vertical transistors0.958
H01L27/1259Multistep manufacturing methods0.958
G01S7/5202for pulse systems0.957
H03K4/026using digital techniques0.957
G01S7/524Transmitters0.957
H03K23/004Counters counting in a non-natural counting order  e.g. random counters0.956
G11C29/50012of timing0.956
G06F12/06Addressing a physical block of locations  e.g. base addressing  module addressing  memory dedication | (ref: G06F12/08)|  takes precedence0.955
G06F9/30Arrangements for executing machine instructions  e.g. instruction decode | for executing microinstructions | (ref: G06F9/22)0.955
G06F15/7871Reconfiguration support  e.g. configuration loading  configuration switching  or hardware OS0.954
H01L27/105including field-effect components0.954
H01L24/97the devices being connected to a common substrate  e.g. interposer  said common substrate being separable into individual assemblies after connecting0.954
H01L25/0652the devices being arranged next and on each other  i.e. mixed assemblies0.954
G11C29/88with partially good memories0.954
G11C29/808using a flexible replacement scheme0.953
F21V17/104using feather joints  e.g. tongues and grooves  with or without friction0.952
G06F1/04Generating or distributing clock signals or signals derived directly therefrom0.952
H03K3/0372of the master-slave type0.952
H04L27/10Frequency-modulated carrier systems  i.e. using frequency-shift keying | (ref: H04L27/32)|  takes precedence0.946
H03B5/02Details0.946
G11C7/103using serially addressed read-write data registers | (ref: G11C7/1036)|  takes precedence0.945
G11C11/417for memory cells of the field-effect type0.944
H03K17/693Switching arrangements with several input- or output-terminals  e.g. multiplexers  distributors | logic circuits | (ref: H03K19/00)| | code converters | (ref: H03M5/00)|   | (ref: H03M7/00)0.943
H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches | layout of the interconnections | per se|  | (ref: H01L23/528)| | CAD of ICs | (ref: G06F30/00)0.942
H01L21/768Applying interconnections to be used for carrying current between separate components within a device | comprising conductors and dielectrics0.942
G06F11/0751Error or fault detection not based on redundancy | power supply failures | (ref: G06F1/30)| | network fault management | (ref: H04L41/06)0.941
G06F1/22Means for limiting or controlling the pin/gate ratio0.941
G06F1/3268Power saving in hard disk drive0.941
H04N5/907using static stores  e.g. storage tubes or semiconductor memories | (ref: H04N5/91)|  takes precedence0.940
G11C16/3431Circuits or methods to detect disturbed nonvolatile memory cells  e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold  and to reverse the disturbance via a refreshing programming or erasing step0.939
G06F12/0893Caches characterised by their organisation or structure0.939
G06F13/42Bus transfer protocol  e.g. handshake| Synchronisation0.937
G11C11/5678using amorphous/crystalline phase transition storage elements0.937
G11C8/12Group selection circuits  e.g. for memory block selection  chip selection  array selection0.937
G11C29/32Serial access| Scan testing0.937
G06N3/08Learning methods0.936
G06F9/3016Decoding the operand specifier  e.g. specifier format0.936
G06F9/30105Register structure0.936
G06F9/30043LOAD or STORE instructions| Clear instruction0.936
G06F12/0811with multilevel cache hierarchies0.935
G06F21/81by operating on the power supply  e.g. enabling or disabling power-on  sleep or resume operations0.934
G06F30/392Floor-planning or layout  e.g. partitioning or placement0.932
G11C7/065Differential amplifiers of latching type0.931
G11C19/28using semiconductor elements | (ref: G11C19/14)|   | (ref: G11C19/36)|  take precedence0.930
H04L1/205jitter monitoring0.930
G11C17/16using electrically-fusible links0.639
G11C29/789using non-volatile cells or latches0.628
G11C29/838with substitution of defective spares0.628
G11C29/025in signal lines0.628
G11C7/109Control signal input circuits0.628
G11C29/787using a fuse hierarchy0.628
G11C7/1063Control signal output circuits  e.g. status or busy flags  feedback command signals0.628
G06F3/0673Single storage device0.611
G11C29/72with optimized replacement algorithms0.603
G11C16/28using differential sensing or reference cells  e.g. dummy cells0.578
G11C16/24Bit-line control circuits0.578
G11C16/30Power supply circuits0.578
G06F12/0292using tables or multilevel address translation means | (ref: G06F12/023)|  takes precedence| address translation in virtual memory systems | (ref: G06F12/10)0.576
G06F5/06for changing the speed of data flow  i.e. speed regularising | or timing  e.g. delay lines  FIFO buffers| over- or underrun control therefor | (ref: G06F7/78)|  takes precedence0.576
G11C13/0028Word-line or row circuits0.566
H01L45/144Tellurides  e.g. GeSbTe0.566
H01L27/10805with one-transistor one-capacitor memory cells0.566
H01L45/145Oxides or nitrides0.566
G11C7/062Differential amplifiers of non-latching type  e.g. comparators  long-tailed pairs0.557
H03M13/09Error detection only  e.g. using cyclic redundancy check [CRC] codes or single parity bit0.557
G11C11/4082Address Buffers| level conversion circuits0.557
G11C11/1657Word-line or row circuits0.553
G11C19/32using super-conductive elements0.553
G11C11/1655Bit-line or column circuits0.553
G11C11/1693Timing circuits or methods0.553
B82Y10/00Nanotechnology for information processing  storage or transmission  e.g. quantum computing or single electron logic0.553
B82Y20/00Nanooptics  e.g. quantum optics or photonic crystals0.553
B82Y25/00Nanomagnetism  e.g. magnetoimpedance  anisotropic magnetoresistance  giant magnetoresistance or tunneling magnetoresistance0.553
G11C11/16using elements in which the storage effect is based on magnetic spin effect0.553
G06F12/0873Mapping of cache memory to specific storage devices or parts thereof0.551
G06F12/0875with dedicated cache  e.g. instruction or stack0.551
G06F12/1045associated with a data cache0.551
G11C11/2297Power supply circuits0.551
G11C7/1012Data reordering during input/output  e.g. crossbars  layers of multiplexers  shifting or rotating0.551
G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means  e.g. caches0.551
G06F9/546Message passing systems or structures  e.g. queues0.551
G06F3/0629Configuration or reconfiguration of storage systems0.547
G11C7/1093Input synchronization0.542
G11C29/04Detection or location of defective memory elements |   e.g. cell constructio details  timing of test signals0.542
G06F11/3037where the computing system component is a memory  e.g. virtual memory  cache | accessing  addressing or allocating within memory systems or architectures | (ref: G06F12/00)| | checking stores for correct operation | (ref: G11C29/00)0.542
G06F12/1036for multiple virtual address spaces  e.g. segmentation | (ref: G06F12/1045)|  takes precedence0.533
G06F13/1615using a concurrent pipeline structrure0.533
G11C29/44Indication or identification of errors  e.g. for repair0.531
G06F9/30196using decoder  e.g. decoder per instruction set  adaptable or programmable decoders0.531
G11C11/2253Address circuits or decoders0.531
G06F11/0763by bit configuration check  e.g. of formats or tags0.531
G06F11/1072in multilevel memories0.527
G11B20/1833by adding special lists or symbols to the coded information | (ref: G11B20/1806)|   | (ref: G11B20/1866)|  take precedence0.527
G06F9/30018Bit or string instructions| instructions using a mask0.524
G06F9/3001Arithmetic instructions0.524
G06F11/079Root cause analysis  i.e. error or fault diagnosis | in a hardware test environment | (ref: G06F11/22)| | in a software test environment | (ref: G06F11/36)0.521
G06F11/3034where the computing system component is a storage system  e.g. DASD based or network based | digital input from or digital output to record carriers | (ref: G06F3/06)| | digital recording or reproducing | (ref: G11B20/18)| | for distributed storage of data in networks  e.g. transport arrangements for network file system [NFS]  storage area networks [SAN] or network attached storage [NAS]  | (ref: H04L67/1097)0.521
G06F11/141for bus or memory accesses0.521
G06F11/0793Remedial or corrective actions | recovery from an exception in an instruction pipeline | (ref: G06F9/3861)| | by retry | (ref: G06F11/1402)| | for recovering from a failure of a protocol instance or entity | (ref: H04L69/40)0.521
G06F11/0772Means for error signaling  e.g. using interrupts  exception flags  dedicated error registers0.521
G06F11/0766Error or fault reporting or storing0.521
G06F9/542Event management| Broadcasting| Multicasting| Notifications0.518
G11C16/3495Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices  e.g. by counting numbers of erase or reprogram cycles  by using multiple memory areas serially or cyclically0.518
G06F9/30098Register arrangements0.518
G06F3/0683Plurality of storage devices0.514
G06F3/0614Improving the reliability of storage systems0.514
G06F21/79in semiconductor storage media  e.g. directly-addressable memories0.514
G06F3/0634by changing the state or mode of one or more devices0.514
G11C7/225Clock input buffers0.512
H03K19/20characterised by logic function  e.g. AND  OR  NOR  NOT circuits | (ref: H03K19/003)|  - | (ref: H03K19/01)|  take precedence0.509
H03K19/215using field-effect transistors0.509
G11C11/404with one charge-transfer gate  e.g. MOS transistor  per cell0.509
G06F21/14against software analysis or reverse engineering  e.g. by obfuscation0.508
H02M3/077with parallel connected charge pump stages0.507
G11C29/023in clock generator or timing circuitry0.501
B41J2/04586controlling heads of a type not covered by groups | (ref: B41J2/04575)|  - | (ref: B41J2/04585)|   or of an undefined type0.501
G06F13/4291using a clocked protocol0.496
G11C13/0064Verifying circuits or methods0.495
G11C29/1201comprising I/O circuitry0.495
G11C29/16using microprogrammed units  e.g. state machines0.495
G11C29/12015comprising clock generation or timing circuitry0.495
G06F1/324by lowering clock frequency0.494
G06F1/10Distribution of clock signals |   e.g. skew0.494
G06N3/0454using a combination of multiple neural nets0.491
H01L27/11521characterised by the memory core region | three-dimensional arrangements | (ref: H01L27/11551)0.490
H01L29/42328with at least one additional gate other than the floating gate and the control gate  e.g. program gate  erase gate or select gate0.490
G11C11/2255Bit-line or column circuits0.489
G06F12/1081for peripheral access to main memory  e.g. direct memory access [DMA]0.485
G11C16/16for erasing blocks  e.g. arrays  words  groups0.485
G06F3/0649Lifecycle management0.485
G06F11/3419by assessing time0.485
G06F3/0671In-line storage system0.485
G06F3/0605by facilitating the interaction with a user or administrator0.485
H03M13/152Bose-Chaudhuri-Hocquenghem [BCH] codes0.484
G06F12/0862with prefetch0.484
G06F13/1631through address comparison0.484
G06F12/0842for multiprocessing or multitasking0.484
G11C29/54Arrangements for designing test circuits  e.g. design for test [DFT] tools0.484
G11C29/024in decoders0.484
B41J2/04521reducing number of signal lines needed0.483
B41J2/01Ink jet0.483
G11C13/0097Erasing  e.g. resetting  circuits or methods0.483
H03K7/02Amplitude modulation  i.e. PAM0.482
G11C11/4099Dummy cell treatment| Reference voltage generators0.482
G11C11/5657using ferroelectric storage elements0.482
G06F21/604Tools and structures for managing or administering access control systems0.481
G06F3/0638Organizing or formatting or addressing of data0.481
H04L9/32including means for verifying the identity or authority of a user of the system | or for message authentication  e.g. authorization  entity authentication  data integrity or data verification  non-repudiation  key authentication or verification of credentials| network architectures or network communication protocols for supporting entities authentication in a packet data network | (ref: H04L63/08)| | applying verification of the received information | (ref: H04L63/12)| | |  computer systems | (ref: G06F)| | coin-freed or like apparatus with coded identity card or credit card | (ref: G07F7/08)0.481
G06F21/30Authentication  i.e. establishing the identity or authorisation of security principals0.481
G06F9/35Indirect addressing |   i.e. using single address operand  e.g. address register0.479
G06F9/3004to perform operations on memory0.479
G06F9/30109having multiple operands in a single register0.479
G06F9/30101Special purpose registers0.479
G06F9/3013according to data content  e.g. floating-point registers  address registers0.479
G06F15/8076Details on data register access0.479
G06F1/3237by disabling clock generation or distribution0.479
G11C11/565using capacitive charge storage elements0.477
G06N3/04Architectures  e.g. interconnection topology0.475
G06F1/3203Power management  i.e. event-based initiation of a power-saving mode0.475
G11C16/0466comprising cells with charge storage in an insulating layer  e.g. metal-nitride-oxide-silicon [MNOS]  silicon-oxide-nitride-oxide-silicon [SONOS] | (ref: G11C16/0483)|   | (ref: G11C16/0491)|  take precedence0.475
G06N3/02using neural network models0.472
G01K1/024for remote indication0.471
G06F13/4086Bus impedance matching  e.g. termination0.470
H03M13/45Soft decoding  i.e. using symbol reliability information | (ref: H03M13/41)|  takes precedence0.468
H03M13/19Single error correction without using particular properties of the cyclic codes  e.g. Hamming codes  extended or generalised Hamming codes0.468
G11C29/702by replacing auxiliary circuits  e.g. spare voltage generators  decoders or sense amplifiers  to be used instead of defective ones0.468
H03M13/1575Direct decoding  e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes  e.g. for codes with a small minimum Hamming distance0.468
H03M13/6575Implementations based on combinatorial logic  e.g. Boolean circuits0.468
G11C13/0061Timing circuits or methods0.466
G06F12/0831using a bus scheme  e.g. with bus monitoring or watching means0.466
G06F3/0646Horizontal data movement in storage systems  i.e. moving data in between storage devices or systems0.466
H04L7/0004Initialisation of the receiver | (ref: H04L7/0075)|  and | (ref: H04L7/10)|  take precedence0.465
G01R23/15Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values  by making use of non-linear or digital elements | (indicating that pulse width is above or below a certain limit)0.465
H04L7/0008Synchronisation information channels  e.g. clock distribution lines0.465
G06F15/7839with memory0.465
G06F9/45533Hypervisors| Virtual machine monitors0.464
G06F11/0721within a central processing unit [CPU]0.461
G11C5/144Detection of predetermined disconnection or reduction of power supply  e.g. power down or power standby0.461
G11C5/141Battery and back-up supplies0.461
H01L24/06of a plurality of bonding areas0.460
G06N3/0481Non-linear activation functions  e.g. sigmoids  thresholds0.460
G11C11/1673Reading or sensing circuits or methods0.460
G11C11/5671using charge trapping in an insulator0.459
G11C7/1096Write circuits  e.g. I/O line write drivers0.457
H04L1/0046Code rate detection or code type detection | (ref: H04L1/0038)|  takes precedence| detection of the data rate | (ref: H04L25/0262)| | for packet format | (ref: H04L1/0091)0.457
H04L1/0014by adapting the source coding0.457
G11C11/56using storage elements with more than two stable states represented by steps  e.g. of voltage  current  phase  frequency0.457
H04L25/0282Provision for current-mode coupling0.457
H01L27/11524with cell select transistors  e.g. NAND0.456
H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate  e.g. cross-point arrays  details of the horizontal layout0.456
H01L27/11502with ferroelectric memory capacitors0.456
H01L27/222Magnetic non-volatile memory structures  e.g. MRAM0.456
H01L23/38Cooling arrangements using the Peltier effect0.456
H01L27/11551characterised by three-dimensional arrangements  e.g. with cells on different height levels0.456
H01L23/34Arrangements for cooling  heating  ventilating or temperature compensation | | Temperature sensing arrangements | thermal treatment apparatus | (ref: H01L21/00)0.456
H01L27/11585with the gate electrodes comprising a layer used for its ferroelectric memory properties  e.g. metal-ferroelectric-semiconductor [MFS] or metal-ferroelectric-metal-insulator-semiconductor [MFMIS]0.456
H01L27/11578characterised by three-dimensional arrangements  e.g. with cells on different height levels0.456
H01L27/10844Multistep manufacturing methods0.456
G11C7/14Dummy cell management| Sense reference voltage generators0.456
H03K19/17752for hot reconfiguration0.453
G06F11/183by voting  the voting not being performed by the redundant components0.453
G06F11/104using arithmetic codes  i.e. codes which are preserved during operation  e.g. modulo 9 or 11 check0.453
G11C13/0023Address circuits or decoders0.452
G06F9/3455using stride0.452
G06F11/3058Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component  e.g. monitoring of power  currents  temperature  humidity  position  vibrations | thermal management in cooling arrangements of a computing system | (ref: G06F1/206)0.452
G06F9/5094where the allocation takes into account power or heat criteria | power management in computers in general | (ref: G06F1/3203)| | thermal management in computers in general | (ref: G06F1/206)0.451
G06F1/20Cooling means0.451
G06F13/40Bus structure | for computer networks | (ref: G06F15/163)| | for optical bus networks | (ref: H04B10/25)0.451
G06F3/0635by changing the path  e.g. traffic rerouting  path reconfiguration0.451
B41J2/04563detecting head temperature| Ink temperature0.450
B41J2/04551using several operating modes0.450
H03M13/1515Reed-Solomon codes0.448
H03M13/1102Codes on graphs and decoding on graphs  e.g. low-density parity check [LDPC] codes0.448
G06F3/0644Management of space entities  e.g. partitions  extents  pools0.448
G11C29/846by choosing redundant lines at an output stage0.447
G06F3/0647Migration mechanisms0.447
G06F11/108Parity data distribution in semiconductor storages  e.g. in SSD0.447
G11C29/74using duplex memories  i.e. using dual copies0.447
H01L27/10885with at least one step of making a bit line0.444
H01L27/10888with at least one step of making a bit line contact0.444
H01L27/10891with at least one step of making a word line0.444
H01L27/0688Integrated circuits having a three-dimensional layout0.444
H01L27/10894with simultaneous manufacture of periphery and memory cells0.444
G06F3/05Digital input using the sampling of an analogue quantity at regular intervals of time |   input from a/d converter or output to d/a converter0.444
G11C19/00Digital stores in which the information is moved stepwise  e.g. shift registers0.444
G11C17/165Memory cells which are electrically programmed to cause a change in resistance  e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses | digital stores using resistance random access memory elements | (ref: G11C13/0002)0.443
H03K19/21EXCLUSIVE-OR circuits  i.e. giving output if input signal exists at only one input| COINCIDENCE circuits  i.e. giving output only if all input signals are identical0.443
G06F7/588Random number generators  i.e. based on natural stochastic processes0.443
G11C16/0433comprising cells containing a single floating gate transistor and one or more separate select transistors0.442
G09G3/006Electronic inspection or testing of displays and display drivers  e.g. of LED or LCD displays | testing individual LED's | (ref: G01R31/2635)| | testing lamps | (ref: G01R31/44)| | testing of optical features of LCD displays | (ref: G02F1/1309)0.439
G06F12/1009using page tables  e.g. page table structures0.436
G11C29/12005comprising voltage or current generators0.435
H03K3/037Bistable circuits0.434
G11C27/005with non-volatile charge storage  e.g. on floating gate or MNOS0.428
H01L29/42344with at least one additional gate  e.g. program gate  erase gate or select gate0.428
H01L29/7883charging by tunnelling of carriers  e.g. Fowler-Nordheim tunnelling0.428
G06F21/76in application-specific integrated circuits [ASICs] or field-programmable devices  e.g. field-programmable gate arrays [FPGAs] or programmable logic devices [PLDs]0.427
H01L29/42324Gate electrodes for transistors with a floating gate0.425
H04L9/0643Hash functions  e.g. MD5  SHA  HMAC or f9 MAC0.421
G06F21/57Certifying or maintaining trusted computer platforms  e.g. secure boots or power-downs  version controls  system software checks  secure updates or assessing vulnerabilities0.421
H04L9/0866involving user or device identifiers  e.g. serial number  physical or biometrical information  DNA  hand-signature or measurable physical characteristics0.421
G06K9/6256Obtaining sets of training patterns| Bootstrap methods  e.g. bagging  boosting0.421
H01L27/11514characterised by the three-dimensional arrangements  e.g. with cells on different height levels0.420
H01L29/7841with floating body  e.g. programmable transistors0.420
G11C29/26Accessing multiple arrays | (ref: G11C29/24)|  takes precedence0.420
G11C16/3418Disturbance prevention or evaluation| Refreshing of disturbed memory data0.419
G06F13/362with centralised access control0.418
G06F13/18based on priority control | (ref: G06F13/1605)|  takes precedence0.418
G06F13/1605based on arbitration | arbitration in handling access to a common bus or bus system | (ref: G06F13/36)0.418
G11C11/2293Timing circuits or methods0.418
H01L27/11507characterised by the memory core region0.418
G11C14/00Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down0.418
G01F23/804containing circuits handling parameters other than liquid level0.418
B41J2/17556Means for regulating the pressure in the cartridge0.418
B41J2/17553Outer structure0.418
B41J2/1753Details of contacts on the cartridge  e.g. protection of contacts0.418
B41J2/17526Electrical contacts to the cartridge0.418
G01F23/247for discrete levels0.418
G01F23/802Particular electronic circuits for digital processing equipment0.418
G01F25/20of apparatus for measuring liquid level0.418
G01L5/1627of strain gauges | using piezoresistors | (ref: G01L5/162)0.418
B41J2/17513Inner structure0.418
B41J2/04546Multiplexing0.418
B41J2/04508aiming at correcting other parameters0.418
B33Y30/00Apparatus for additive manufacturing| Details thereof or accessories therefor0.418
H03K19/017509Interface arrangements0.418
B29C64/259Interchangeable0.418
G06F21/60Protecting data0.418
G06F1/12Synchronisation of different clock signals | provided by a plurality of clock generators0.418
G06F21/85interconnection devices  e.g. bus-connected or in-line devices0.418
G06F3/121Facilitating exception or error detection and recovery  e.g. fault  media or consumables depleted0.418
B41J2/14201Structure of print heads with piezoelectric elements0.417
G06F21/445by mutual authentication  e.g. between devices or programs0.417
H04N1/32101Display  printing  storage or transmission of additional information  e.g. ID code  date and time or title0.417
G06F21/84output devices  e.g. displays or monitors0.417
G06F13/00Interconnection of  or transfer of information or other signals between  memories  input/output devices or central processing units | interface circuits for specific input/output devices  | (ref: G06F3/00)| | multiprocessor systems  | (ref: G06F15/16)|  | multiprogram control therefor  | (ref: G06F9/46)0.417
G09G5/006Details of the interface to the display terminal | specific for a display terminal using a CRT | (ref: G09G1/167)| | using a flat panel | (ref: G09G3/2096)| | circuits for interfacing with colour displays | (ref: G09G5/04)0.416
H05B47/105in response to determined parameters0.416
H05B47/125by using cameras0.416
H05B45/20Controlling the colour of the light0.416
H05B47/18via data-bus transmission0.416
G11C29/56004Pattern generation0.415
H04L1/0003by switching between different modulation schemes0.415
G09G3/3233with pixel circuitry controlling the current through the light-emitting element0.413
H03M13/31combining coding for error detection or correction and efficient use of the spectrum | without error detection or correction | (ref: H03M5/14)|   |   | (ref: H03M5/145)0.412
H03M13/616Matrix operations  especially for generator matrices or check matrices  e.g. column or row permutations0.412
G06F11/102Error in check bits0.412
H01L27/2436comprising multi-terminal selection components  e.g. transistors0.412
H01L45/1233adapted for essentially vertical current flow  e.g. sandwich or pillar type devices0.412
H01L45/04Bistable or multistable switching devices  e.g. for resistance switching non-volatile memory0.412
H01L45/06based on solid-state phase change  e.g. between amorphous and crystalline phases  Ovshinsky effect0.412
G11C16/3445Circuits or methods to verify correct erasure of nonvolatile memory cells0.412
G06F11/16Error detection or correction of the data by redundancy in hardware0.411
G06F11/2215to test error correction or detection circuits0.409
G06F12/1425the protection being physical  e.g. cell  word  block0.409
G06F3/0665at area level  e.g. provisioning of virtual or logical volumes0.408
H04L49/351for local area network [LAN]  e.g. Ethernet switches0.408
H04L67/104Peer-to-peer [P2P] networks0.408
H04L67/1044Group management mechanisms  | management of multicast group membership | (ref: H04L12/185)| | reconfiguring of node membership in a computing system to eliminate errors | (ref: G06F11/1425)0.408
H04L9/0819Key transport or distribution  i.e. key establishment techniques where one party creates or otherwise obtains a secret value  and securely transfers it to the other(s) | network architectures or network communication protocols for key distribution in a packet data network | (ref: H04L63/062)0.408
H04L67/1074for supporting data block transmission mechanisms | file transfer | (ref: H04L67/06)0.408
G06N3/049Temporal neural nets  e.g. delay elements  oscillating neurons  pulsed inputs0.408
G11C13/0002using resistive RAM [RRAM] elements0.408
H03M7/165Conversion to or from thermometric code0.407
G11C7/1018Serial bit line access mode  e.g. using bit line address shift registers  bit line address counters  bit line burst counters0.406
G06F12/0866for peripheral storage systems  e.g. disk cache0.405
G06F1/3296by lowering the supply or operating voltage0.405
G06F1/3287by switching off individual functional units in the computer system0.405
G11C29/883using a single defective memory device with reduced capacity  e.g. half capacity0.405
A47G9/007comprising deodorising  fragrance releasing  therapeutic or disinfecting substances0.404
B41J2/14072Electrical connections  e.g. details on electrodes  connecting the chip to the outside...0.404
B41J2/04555detecting current0.404
G06F13/1657Access to multiple memories0.404
G06F13/1647with interleaved bank access0.404
G11C16/06Auxiliary circuits  e.g. for writing into memory0.404
B41J2/17523Ink connection0.402
H01L21/76877Filling of holes  grooves or trenches  e.g. vias  with conductive material0.401
G09G3/2022using sub-frames0.400
G02B27/017Head mounted0.400
G02B27/0172characterised by optical features0.400
H01L24/16of an individual bump connector0.400
H01L25/50Multistep manufacturing processes of assemblies consisting of devices  each device being of a type provided for in group | (ref: H01L27/00)|  or | (ref: H01L29/00)|  | (ref: H01L21/50)|  takes precedence0.400
H01L23/528Geometry or|  layout of the interconnection structure | (ref: H01L27/0207)|  takes precedence| algorithms | (ref: G06F30/00)0.400
H01L24/02Bonding areas | on insulating substrates  e.g. chip carriers  | (ref: H01L23/49816)|   | (ref: H01L23/49838)|   | (ref: H01L23/5389)| | Manufacturing methods related thereto0.400
H01L24/17of a plurality of bump connectors0.400
H01L23/5283Cross-sectional geometry0.400
G06F7/5443Sum of products | for applications thereof  | see|  the relevant places  e.g. | (ref: G06F17/10)|   | (ref: H03H17/00)0.398
H03M7/3059Digital compression and data reduction techniques where the original information is represented by a subset or similar information  e.g. lossy compression0.397
H03M7/3066by means of a mask or a bit-map0.397
G06F17/153Multidimensional correlation or convolution0.397
H01L27/10852the capacitor extending over the access transistor0.396
H01L27/1116Peripheral circuit region0.396
H04N5/351Control of the SSIS depending on the scene  e.g. brightness or motion in the scene0.396
H04N5/2351Circuitry for evaluating the brightness variations of the object | within the image sensor | (ref: H04N5/351)| | photometry in general | (ref: G01J1/00)0.396
G11C7/16Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters  digital memories and digital/analogue [D/A] converters 0.395
G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen | (ref: G09G5/399)|  takes precedence0.393
G11C29/70Masking faults in memories by using spares or by reconfiguring0.393
G09G5/393Arrangements for updating the contents of the bit-mapped memory0.393
G06F12/023Free address space management0.392
H03L7/091the phase or frequency detector using a sampling device | (ref: H03L7/087)|  takes precedence0.391
B82Y30/00Nanotechnology for materials or surface science  e.g. nanocomposites0.391
B01J19/0046Sequential or parallel reactions  e.g. for the synthesis of polypeptides or polynucleotides| Apparatus and devices for combinatorial chemistry or for making molecular arrays | synthesis methods | per se|  | (ref: C40B50/00)0.391
G11C29/56012Timing aspects  clock generation  synchronisation0.390
G11C29/46Test trigger logic0.390
H01L25/105the devices being of a type provided for in group | (ref: H01L27/00)0.390
H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies| Methods or apparatus related thereto0.390
G06F3/0661Format or protocol conversion arrangements0.389
G06F3/0685Hybrid storage combining heterogeneous device types  e.g. hierarchical storage  hybrid arrays0.389
G06F12/0868Data transfer between cache memory and other subsystems  e.g. storage devices or host systems0.389
G06F3/068Hybrid storage device0.389
G01S7/487Extracting wanted echo signals |   e.g. pulse detection0.388
G01S7/4914of detector arrays  e.g. charge-transfer gates0.388
G01S7/4911Transmitters0.388
G01S17/14wherein a voltage or current pulse is initiated and terminated in accordance with the pulse transmission and echo reception respectively  e.g. using counters0.388
G01S7/484Transmitters0.388
G01S7/4811common to transmitter and receiver0.388
G11C16/0416comprising cells containing a single floating gate transistor and no select transistor  e.g. UV EPROM0.388
B60L3/12Recording operating variables | | Monitoring of operating variables0.387
H02P3/12by short-circuit or resistive braking0.387
H02P3/22by short-circuit or resistive braking0.387
H02P27/06using dc to ac converters or inverters | (ref: H02P27/05)|  takes precedence0.387
H02P29/00Arrangements for regulating or controlling electric motors  appropriate for both AC and DC motors | arrangements for starting electric motors | (ref: H02P1/00)| | arrangements for stopping or slowing electric motors | (ref: H02P3/00)| | control of motors that can be connected to two or more different electric power supplies | (ref: H02P4/00)| | regulating or controlling the speed or torque of two or more electric motors | (ref: H02P5/00)| | vector control | (ref: H02P21/00)0.387
H02P29/024Detecting a fault condition  e.g. short circuit  locked rotor  open circuit or loss of load0.387
H02P29/028the motor continuing operation despite the fault condition  e.g. eliminating  compensating for or remedying the fault0.387
B60T8/32responsive to a speed condition  e.g. acceleration or deceleration | using electrical circuitry or regulation means | (ref: B60T8/17)|  | | (ref: B60T8/28)|  takes precedence| electric devices on electrically propelled vehicles indicating the wheel slip | (ref: B60L3/10)| | measuring linear or angular speed | per se|  | (ref: G01P3/00)0.387
B60L3/04Cutting off the power supply under fault conditions | protective devices and circuit arrangements in general | (ref: H01H)| | | (ref: H02H)0.387
B60L3/0084relating to control modules0.387
B60L3/003relating to inverters0.387
G06F1/14Time supervision arrangements  e.g. real time clock0.387
G06F13/1663Access to shared memory0.387
H03K19/1737using multiplexers | (ref: H03K19/1738)|  takes precedence0.386
G06F12/0253Garbage collection  i.e. reclamation of unreferenced memory0.385
G06F12/10Address translation0.385
H04L9/002Countermeasures against attacks on cryptographic mechanisms | network architectures or network communication protocols for protection against malicious traffic | (ref: H04L63/1441)0.385
H04L9/3242involving keyed hash functions  e.g. message authentication codes [MACs]  CBC-MAC or HMAC0.385
G06F7/582Pseudo-random number generators0.385
H04L63/1466Active attacks involving interception  injection  modification  spoofing of data unit addresses  e.g. hijacking  packet injection or TCP sequence number attacks0.385
H04L63/08for supporting authentication of entities communicating through a packet data network | cryptographic mechanisms or cryptographic arrangements for entity authentication | (ref: H04L9/32)0.385
H04L63/126the source of the received data0.385
H04L9/0841involving Diffie-Hellman or related key agreement protocols0.385
H04L9/0897involving additional devices  e.g. trusted platform module [TPM]  smartcard or USB0.385
G06F8/60Software deployment0.385
G06F9/30003Arrangements for executing specific machine instructions0.385
G06F9/441Multiboot arrangements  i.e. selecting an operating system to be loaded0.385
G06F21/33using certificates0.385
H04L9/3271using challenge-response0.385
H04L9/3234involving additional secure or trusted devices  e.g. TPM  smartcard  USB or software token | network architectures or network communication protocols for supporting authentication of entities using an additional device in a packet data network | (ref: H04L63/0853)0.385
G06F11/0736in functional embedded systems  i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function | testing or monitoring of automated control systems | (ref: G05B23/02)0.384
G06F12/123with age lists  e.g. queue  most recently used [MRU] list or least recently used [LRU] list0.384
H02J7/0014Circuits for equalisation of charge between batteries0.384
H02J7/0068Battery or charger load switching  e.g. concurrent charging and load supply | (ref: H02J7/0013)|  takes precedence0.384
G06F9/4406Loading of operating system0.384
H02J7/0047with monitoring or indicating devices or circuits0.384
H01M10/425Structural combination with electronic components  e.g. electronic circuits integrated to the outside of the casing | printed circuits | (ref: H05K1/00)0.384
G06F9/4401Bootstrapping | security arrangements therefor | (ref: G06F21/57)0.384
G11C13/0007comprising metal oxide memory material  e.g. perovskites0.384
H01L29/792with charge trapping gate insulator  e.g. MNOS-memory transistors0.384
H01L45/146Binary metal oxides  e.g. TaOx0.384
H01L29/66833with a charge trapping gate insulator  e.g. MNOS transistors0.384
G06F3/0652Erasing  e.g. deleting  data cleaning  moving of data to a wastebasket0.384
G11C29/38Response verification devices0.383
G11C29/785with redundancy programming schemes0.383
H01L23/49827Via connections through the substrates  e.g. pins going through the substrate  coaxial cables | (ref: H01L23/49822)|   | (ref: H01L23/49833)|   | (ref: H01L23/4985)|   | (ref: H01L23/49861)|  take precedence0.383
H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment  or specially adapted for reliability measurements0.383
G11C16/3436Arrangements for verifying correct programming or erasure0.382
G11C17/00Read-only memories programmable only once| Semi-permanent stores  e.g. manually-replaceable information cards0.382
G06F15/7882for self reconfiguration0.381
H04N5/367applied to defects  e.g. non-responsive pixels0.381
G01R31/2829Testing of circuits in sensor or actuator systems | testing of apparatus for measuring electric or magnetic variables | (ref: G01R35/00)| | testing of indicating or recording apparatus | (ref: G01D)| | in airbag systems | (ref: B60R21/0173)| | checking gas analysers | (ref: G01N33/007)| | monitoring or fail-safe circuits for electromagnets | (ref: H01F7/1844)0.381
G01R31/52Testing for short-circuits  leakage current or ground faults0.381
G01R31/54Testing for continuity0.381
G11C7/1021Page serial bit line access mode  i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address0.381
H01L45/1683by filling of openings  e.g. damascene method0.381
H01L45/16Manufacturing0.381
H01L45/1226adapted for essentially horizontal current flow  e.g. bridge type devices0.381
H01L23/5384Conductive vias through the substrate with or without pins  e.g. buried coaxial conductors | (ref: H01L23/5383)|   | (ref: H01L23/5385)|  take precedence| pins attached to insulating substrates | (ref: H01L23/49811)0.380
H01L21/76898formed through a semiconductor substrate0.379
H03F3/195in integrated circuits0.378
H03F3/2178using more than one switch or switching amplifier in parallel or in series | (ref: H03F3/2173)|   | (ref: H03F3/2175)|  take precedence0.378
H04L27/2017in which the phase changes are non-linear  e.g. generalized and Gaussian minimum shift keying  tamed frequency modulation | (ref: H04L27/201)|  takes precedence0.378
H03B5/1206using multiple transistors for amplification0.378
H03F3/245with semiconductor devices only0.378
H04L27/3405Modifications of the signal space to increase the efficiency of transmission  e.g. reduction of the bit error rate  bandwidth  or average power0.378
H03F1/0211with control of the supply voltage or current0.378
H03F3/21with semiconductor devices only | (ref: H03F3/245)|  takes precedence0.378
G02B26/0833the reflecting element being a micromechanical device  e.g. a MEMS mirror  DMD | (ref: G02B26/0825)|  takes precedence| micromechanical devices in general | (ref: B81B)0.378
G09G3/346based on modulation of the reflection angle  e.g. micromirrors | micromirrors devices | per se|  | (ref: G02B26/0833)0.378
H02M3/073Charge pumps of the Schenkel-type0.377
H03L5/00Automatic control of voltage  current  or power0.377
G05F1/571with overvoltage detector0.377
G05F1/575characterised by the feedback circuit0.377
G05F1/59including plural semiconductor devices as final control devices for a single load0.377
H02N13/00Clutches or holding devices using electrostatic attraction  e.g. using Johnson-Rahbek effect0.377
G06F9/30094Condition code generation  e.g. Carry  Zero flag0.377
G06F9/355Indexed addressing |   i.e. using more than one address operand0.377
G06F11/201between storage system components0.376
G06F12/0897with two or more cache hierarchy levels | with multilevel cache hierarchies | (ref: G06F12/0811)0.376
H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass | circuits with regenerative action | (ref: H03K3/00)|   | (ref: H03K4/00)| | by the use of non-linear magnetic or dielectric devices | (ref: H03K3/45)0.376
G06F21/554involving event detection and direct action0.376
G08B21/185Electrical failure alarms0.376
G01R19/30Measuring the maximum or the minimum value of current or voltage reached in a time interval | (ref: G01R19/04)|  takes precedence0.376
G01R19/1659to indicate that the value is within or outside a predetermined range of values (window) | (ref: G01R19/16514)|   | (ref: G01R19/16519)|   | (ref: G01R19/16528)|  and | (ref: G01R19/16533)|  take precedence0.376
G06F21/75by inhibiting the analysis of circuitry or operation0.376
G01R19/0038Circuits for comparing several input signals and for indicating the result of this comparison  e.g. equal  different  greater  smaller (comparing pulses or pulse trains according to amplitude)0.376
G09G3/2096Details of the interface to the display terminal specific for a flat panel | suitable for both CRT and flat panel | (ref: G09G5/006)| | specific for a CRT | (ref: G09G1/167)0.375
H05B47/22with communication between the lamps and a central unit0.375
H05B39/047with pulse width modulation from a DC power source0.375
H05B47/19via wireless transmission0.375
H01L21/823475interconnection or wiring or contact manufacturing related aspects0.375
H01L29/4234Gate electrodes for transistors with charge trapping gate insulator0.375
H01L27/11575characterised by the boundary region between the core and peripheral circuit regions0.375
H01L29/1033with insulated gate  e.g. characterised by the length  the width  the geometric contour or the doping structure | with channel and gate aligned in the lengthwise direction | (ref: H01L29/42376)| | with buried channel | (ref: H01L29/7838)0.375
H01L27/11519characterised by the top-view layout0.375
H01L27/11573characterised by the peripheral circuit region0.375
G06F13/409Mechanical coupling | back panels | (ref: H05K7/1438)0.374
G11C7/1003Interface circuits for daisy chain or ring bus memory arrangements0.374
G01R31/26Testing of individual semiconductor devices | testing or measuring during manufacture or treatment | (ref: H01L22/00)| | testing of photovoltaic devices | (ref: H02S50/10)0.374
H04N5/37457comprising amplifiers shared between a plurality of pixels  e.g. at least one part of the amplifier has to be on the sensor array itself0.374
H04N5/3698Circuitry for controlling the generation or the management of the power supply0.374
H04N5/3559by controlling the amount of charge storable in the pixel  e.g. modification of the charge conversion ratio of the floating node capacitance0.374
H04N5/35554with different integration times0.374
H04N5/379Details of the architecture or circuitry being divided to different or multiple substrates  chips or circuit boards  e.g. stacked image sensors | line sensors | (ref: H04N5/3694)0.374
H04N5/3454by reading contiguous pixels in two directions within a read portion of the array  e.g. without loss of resolution in two directions  windowing or electronic zooming0.374
H03M13/2906using block codes | (ref: H03M13/2957)|  takes precedence0.374
H01L24/48of an individual wire connector0.373
H01L23/3128the substrate having spherical bumps for external connection0.373
H01L23/49816Spherical bumps on the substrate for external connection  e.g. ball grid arrays [BGA]0.373
H01L23/3135Double encapsulation or coating and encapsulation0.373
H01L29/786Thin film transistors  | i.e. transistors with a channel being at least partly a thin film | transistors having only the source or the drain region on an insulator layer | (ref: H01L29/0653)| | thin film FinFETs | (ref: H01L29/785)0.372
H01L23/50for integrated circuit devices  | e.g. power bus  number of leads| (ref: H01L23/482)|  - | (ref: H01L23/498)|  take precedence0.372
G11C13/0011comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]0.372
G09C1/00Apparatus or methods whereby a given sequence of signs  e.g. an intelligible text  is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system | cryptographic typewriters | (ref: G09C3/00)0.372
G06F12/0853Cache with multiport tag or data arrays0.372
H04N5/357Noise processing  e.g. detecting  correcting  reducing or removing noise0.372
H04N5/3745having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix  e.g. memories  A/D converters  pixel amplifiers  shared circuits or shared components0.372
G06F13/24using interrupt | (ref: G06F13/32)|  takes precedence0.371
G06F12/122of the least frequently used [LFU] type  e.g. with individual count value0.371
G11C11/5664using organic memory material storage elements0.371
G05B11/42for obtaining a characteristic which is both proportional and time-dependent  e.g. P.I.  P.I.D.0.371
G06F12/0895of parts of caches  e.g. directory or tag array0.370
H04L9/088Usage controlling of secret information  e.g. techniques for restricting cryptographic keys to pre-authorized uses  different access levels  validity of crypto-period  different key- or password length  or different strong and weak cryptographic algorithms | network architectures or network communication protocols for using time-dependent keys in a packet data network | (ref: H04L63/068)0.370
H04L9/0894Escrow  recovery or storing of secret information  e.g. secret key escrow or cryptographic key storage0.370
G06F12/1491in a hierarchical protection system  e.g. privilege levels  memory rings0.370
G06F12/0864using pseudo-associative means  e.g. set-associative or hashing0.370
G06F3/0482Interaction with lists of selectable items  e.g. menus0.369
G06F9/4403Processor initialisation0.369
G06T1/20Processor architectures| Processor configuration  e.g. pipelining0.369
G06F3/0481based on specific properties of the displayed interaction object or a metaphor-based environment  e.g. interaction with desktop elements like windows or icons  or assisted by a cursor's changing behaviour or appearance0.369
G06F3/04847Interaction techniques to control parameter settings  e.g. interaction with sliders or dials0.369
G11C5/10for interconnecting capacitors0.368
H03K17/102in field-effect transistor switches0.367
H03K17/08128in composite switches0.367
H03K17/10Modifications for increasing the maximum permissible switched voltage0.367
H03K17/284in field effect transistor switches0.367
H03K17/567Circuits characterised by the use of more than one type of semiconductor device  e.g. BIMOS  composite devices such as IGBT0.367
H03K17/689with galvanic isolation between the control circuit and the output circuit | (ref: H03K17/78)|  takes precedence0.367
H01L27/14643Photodiode arrays| MOS imagers0.367
H01L31/02027for devices working in avalanche mode0.367
G01S7/4861Circuits for detection  sampling  integration or read-out0.367
H03M1/365the voltage divider being a single resistor string0.366
G11C29/816for an application-specific layout0.366
H04L41/145involving simulating  designing  planning or modelling of a network0.366
H04L12/40039Details regarding the setting of the power status of a node according to activity on the bus0.366
G06F1/3209Monitoring remote activity  e.g. over telephone lines or network connections0.366
G06F13/4239with asynchronous protocol0.365
B41J2/3555Historical control0.364
G01S7/497Means for monitoring or calibrating0.364
G04F10/005Time-to-digital converters [TDC] | analog-to-digital converters with intermediate conversion to time or phase | (ref: H03M1/50)|   | (ref: H03M1/60)0.364
G11C16/3404Convergence or correction of memory cell threshold voltages| Repair or recovery of overerased or overprogrammed cells0.364
G09G3/3674Details of drivers for scan electrodes0.363
H01L27/24including solid state components for rectifying  amplifying or switching without a potential-jump barrier or surface barrier  | e.g. resistance switching non-volatile memory structures0.363
H01L21/185Joining of semiconductor bodies for junction formation0.363
H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups | (ref: H01L21/06)|  - | (ref: H01L21/326)|   | e.g. sealing of a cap to a base of a container0.363
H01L24/73Means for bonding being of different types provided for in two or more of groups | (ref: H01L24/10)|   | (ref: H01L24/18)|   | (ref: H01L24/26)|   | (ref: H01L24/34)|   | (ref: H01L24/42)|   | (ref: H01L24/50)|   | (ref: H01L24/63)|   | (ref: H01L24/71)0.363
H01L29/04characterised by their crystalline structure  e.g. polycrystalline  cubic or particular orientation of crystalline planes | characterised  by physical imperfections | (ref: H01L29/30)0.363
H01L24/83using a layer connector0.363
H01L29/16including  apart from doping materials or other impurities  only elements of Group IV of the Periodic System0.363
H01L27/10873with at least one step of making the transistor0.363
H01L27/10847for structures comprising one transistor one-capacitor memory cells0.363
H01L27/10808the storage electrode stacked over transistor0.363
H01L24/03Manufacturing methods0.363
H01L24/05of an individual bonding area0.363
H01L24/08of an individual bonding area0.363
H01L24/26Layer connectors  e.g. plate connectors  solder or adhesive layers| Manufacturing methods related thereto0.363
H01L24/27Manufacturing methods0.363
H01L24/32of an individual layer connector0.363
H01L27/11526characterised by the peripheral circuit region0.363
H01L23/66High-frequency adaptations0.363
H01L23/5386Geometry or layout of the interconnection structure0.363
H04L1/0057Block codes | (ref: H04L1/0061)|   | (ref: H04L1/0064)|  take precedence0.363
H03M7/6023Parallelization0.363
H04L1/0041Arrangements at the transmitter end0.363
G06F7/724Finite field arithmetic | for error detection or correction in general | (ref: H03M13/00)|   in computers | (ref: G06F11/10)0.362
G01L1/18using properties of piezo-resistive materials  i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material0.362
G01L1/146for measuring force distributions  e.g. using force arrays | (ref: G01L1/148)|  takes precedence0.362
G01L5/009Force sensors associated with material gripping devices0.362
G01L1/205using distributed sensing elements0.362
G01L5/228using tactile array force sensors0.362
G01L1/225Measuring circuits therefor0.362
G01R31/3177Testing of logic operation  e.g. by logic analysers0.362
G11C11/4045using a plurality of serially connected access transistors  each having a storage capacitor0.362
H03K23/44using field-effect transistors | (ref: H03K23/46)|  and | (ref: H03K23/425)|  take precedence0.362
H03K25/02comprising charge storage  e.g. capacitor without polarisation hysteresis0.362
G11C11/24using capacitors | (ref: G11C11/22)|  takes precedence| using a combination of semiconductor devices and capacitors | (ref: G11C11/34)|   e.g. | (ref: G11C11/40)0.362
G11C7/1027Static column decode serial bit line access mode  i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses0.362
H01L29/4011for data storage electrodes0.362
H01L29/407Recessed field plates  e.g. trench field plates  buried field plates0.362
H01L29/7827Vertical transistors | (ref: H01L29/7802)|   | (ref: H01L29/78642)|  take precedence0.362
H01L29/0649Dielectric regions  e.g. SiO| 2|  regions  air gaps0.362
H01L27/11548characterised by the boundary region between the core and peripheral circuit regions0.362
H05B45/00Circuit arrangements for operating light emitting diodes [LEDs]0.362
G09G3/2003Display of colours | specific for liquid crystal displays | (ref: G09G3/3607)0.362
G09G3/2088with use of a plurality of processors  each processor controlling a number of individual elements of the matrix0.362
F21V23/0478by means of an image recording device  e.g. a camera0.362
F21S41/141Light emitting diodes [LED]0.362
H03M1/42Sequential comparisons in series-connected stages with no change in value of analogue signal0.362
H03M1/785using resistors  i.e. R-2R ladders0.362
H03M1/802using capacitors  e.g. neuron-mos transistors  charge coupled devices0.362
H03M9/00Parallel/series conversion or | vice versa|  | digital stores in which the information is moved stepwise | per se|  | (ref: G11C19/00)0.361
G06F7/50Adding| Subtracting | (ref: G06F7/483)|  - | (ref: G06F7/491)|   | (ref: G06F7/544)|  - | (ref: G06F7/556)|  take precedence0.361
G06F7/523Multiplying only0.361
G11C7/1015Read-write modes for single port memories  i.e. having either a random port or a serial port0.361
G09G3/3216using a passive matrix0.361
H01L25/167comprising optoelectronic devices  e.g. LED  photodiodes0.361
H01L27/124with a particular composition  shape or layout of the wiring layers specially adapted to the circuit arrangement  e.g. scanning lines in LCD pixel circuits | wiring structures | per se|  | (ref: H01L23/52)0.361
H03L7/102the additional signal being directly applied to the controlled loop oscillator0.360
H03L1/023by using voltage variable capacitance diodes0.360
H03L7/093using special filtering or amplification characteristics in the loop | (ref: H03L7/087)|  - | (ref: H03L7/091)|  take precedence0.360
H03L7/101using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop | (ref: H03L7/113)|   | (ref: H03L7/187)|  take precedence0.360
H03L7/07using several loops  e.g. for redundant clock signal generation | for indirect frequency synthesis | (ref: H03L7/22)0.360
H03L7/22using more than one loop0.360
G06F13/4221being an input/output bus  e.g. ISA bus  EISA bus  PCI bus  SCSI bus0.360
G06V10/147Details of sensors  e.g. sensor lenses | fingerprint or palmprint sensors | (ref: G06V40/13)| | vascular sensors | (ref: G06V40/145)| | eye sensors | (ref: G06V40/19)0.359
G09G3/3611Control of matrices with row and column drivers0.359
H01L27/1218with a particular composition or structure of the substrate0.359
H01L29/78696characterised by the structure of the channel  e.g. multichannel  transverse or longitudinal shape  length or width  doping structure  or the overlap or alignment between the channel and the gate  the source or the drain  or the contacting structure of the channel | (ref: H01L29/78612)|  takes precedence| transistors having a drain offset region or a lightly doped drain [LDD] | (ref: H01L29/78621)0.359
H01L29/41733for thin film transistors with insulated gate0.359
H01L29/66742Thin film unipolar transistors0.359
H01L29/401Multistep manufacturing processes0.359
H01L29/42384for thin film field effect transistors  e.g. characterised by the thickness or the shape of the insulator or the dimensions  the shape or the lay-out of the conductor0.359
H01L29/41741for vertical or pseudo-vertical devices0.359
H01L27/1262with a particular formation  treatment or coating of the substrate0.359
H01L27/1222with a particular composition  shape or crystalline structure of the active layer0.359
G09G3/3275Details of drivers for data electrodes0.359
G09G3/3258with pixel circuitry controlling the voltage across the light-emitting element0.359
B06B1/0215for generating pulses  e.g. bursts of oscillations  envelopes0.359
G06F11/263Generation of test inputs  e.g. test vectors  patterns or sequences | | with adaptation of the tested hardware for testability with external testers0.358
G06F11/2221to test input/output devices or peripheral units0.358
G11C29/06Acceleration testing0.358
G06K19/07with integrated circuit chips0.358
G06F13/364using independent requests or grants  e.g. using separated request and grant lines0.358
H01L23/52Arrangements for conducting electric current within the device in operation from one component to another |   i.e. interconnections  e.g. wires  lead frames | optical interconnections | (ref: G02B6/00)0.358
H01L24/42Wire connectors| Manufacturing methods related thereto0.358
H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to  or being formed on  the surface to be connected0.358
H01L24/82by forming build-up interconnects at chip-level  e.g. for high density interconnects [HDI] | interconnection structure between a plurality of semiconductor chips | (ref: H01L23/5389)0.358
H01L21/78with subsequent division of the substrate into plural individual devices | cutting to change the surface-physical characteristics or shape of semiconductor bodies | (ref: H01L21/304)0.358
F21S8/04intended only for mounting on a ceiling or the like overhead structures | (ref: F21S8/02)|  takes precedence| | details of ceiling bases | (ref: F21V21/03)0.357
A61B5/31for electroencephalography [EEG]0.355
A61B5/37Intracranial electroencephalography [IC-EEG]  e.g. electrocorticography [ECoG]0.355
A61B5/0031Implanted circuitry0.355
H04L5/06the signals being represented by different frequencies | combined with time-division multiplexing | (ref: H04L5/26)0.355
H03B5/1203the amplifier being a single transistor0.355
A61B5/293Invasive0.355
A61B5/262Needle electrodes0.355
H03C3/00Angle modulation | (ref: H03C5/00)|   | (ref: H03C7/00)|  take precedence0.355
G11C5/066Means for reducing external access-lines for a semiconductor memory clip  e.g. by multiplexing at least address and data signals0.354
H01L21/743Making of internal connections  substrate contacts0.353
H01L21/84the substrate being other than a semiconductor body  e.g. being an insulating body0.353
G06F9/223Execution means for microinstructions irrespective of the microinstruction function  e.g. decoding of microinstructions and nanoinstructions| timing of microinstructions| programmable logic arrays| delays and fan-out problems0.353
G06F9/38Concurrent instruction execution  e.g. pipeline  look ahead0.353
G06F12/109for multiple virtual address spaces  e.g. segmentation | (ref: G06F12/1036)|  takes precedence0.353
G06F1/3221of disk drive devices0.353
G09G3/3677suitable for active matrices only0.351
G11C16/3422Circuits or methods to evaluate read or write disturbance in nonvolatile memory  without steps to mitigate the problem0.351
G06F9/461Saving or restoring of program or task context0.351
G06F9/30047Prefetch instructions| cache control instructions0.351
G06F9/30123according to context  e.g. thread buffers0.351
G06F9/3824Operand accessing0.351
G06F9/383Operand prefetching | cache prefetching | (ref: G06F12/0862)0.351
G06F12/0813with a network or matrix configuration0.351
G11C7/1036using data shift registers0.350
G06F21/77in smart cards0.350
G06F11/1417Boot up procedures0.350
G06F21/54by adding security routines or objects to programs0.350
G06F30/398Design verification or optimisation  e.g. using design rule check [DRC]  layout versus schematics [LVS] or finite element methods [FEM] | optical proximity correction [OPC] design processes | (ref: G03F1/36)0.349
G11C19/188Organisation of a multiplicity of shift registers  e.g. regeneration  timing or input-output circuits0.349
G01R31/31709Jitter measurements| Jitter generators | measuring jitter  noise figure or signal-to-noise ratio | per se|  | (ref: G01R29/26)| | analysis of tester signals | (ref: G01R31/31901)0.349
G09G5/008Clock recovery0.349
G11C2211/4061Calibration or ate or cycle tuning0.109
G11C2211/4068Voltage or leakage in refresh operations0.106
G11C2211/4065Low level details of refresh operations0.106
G11C2211/4067Refresh in standby or low power modes0.106
G11C2029/4402Internal storage of test result  quality data  chip identification  repair information0.105
G11C29/027in fuses0.105
Y02D10/00Energy efficient computing  e.g. low power processors  power management or thermal management0.103
H03K19/17732Macroblocks0.103
G11C2029/0403during or with feedback to manufacture0.101
G11C2013/0078Write using current through the cell0.096
G11C2013/009Write using potential difference applied between cell electrodes0.096
G11C2013/0045Read using current through the cell0.096
G11C2013/0071Write using write potential applied to access device gate0.096
G11C2213/71Three dimensional array0.094
G11C2213/73Array where access device function  e.g. diode function  being merged with memorizing function of memory element0.094
G06F2212/60Details of cache memory0.092
G06F2212/7211Wear leveling0.092
G06F2212/7201Logical to physical mapping or translation of blocks or pages0.092
G06F2212/72Details relating to flash memory management0.092
G06F2212/1036Life time enhancement0.092
G06F2212/608Details relating to cache mapping0.092
G11C2207/2227Standby or low power modes0.091
Y02D30/50in wire-line communication networks  e.g. low power modes or reduced link rate0.091
G11C2029/0409Online test0.090
G11C2207/105Aspects related to pads  pins or terminals0.089
G06F2212/1028Power efficiency0.089
G06F2212/1024Latency reduction0.089
G11C2207/2209Concurrent read and write | for multi-port memory | (ref: G11C7/1075)0.089
G11C2207/005Transfer gates  i.e. gates coupling the sense amplifier output to data lines  I/O lines or global bit lines0.089
G11C2207/002Isolation gates  i.e. gates coupling bit lines to the sense amplifier0.089
G06F2212/1032Reliability improvement  data loss prevention  degraded operation etc0.088
G06F2201/83the solution involving signatures0.088
G06F2212/7204Capacity control  e.g. partitioning  end-of-life degradation0.088
G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously0.088
G11C2029/0411Online error correction0.088
G06F9/30032Movement instructions  e.g. MOVE  SHIFT  ROTATE  SHUFFLE0.087
G11C2029/1802Address decoder0.087
G06F11/0703Error or fault processing not based on redundancy  i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation  in hardware  or in data representation0.087
G06F2201/82Solving problems relating to consistency | ensuring consistency in mirrored systems | (ref: G06F11/2064)0.087
G06F11/004Error avoidance | (ref: G06F11/07)|  and subgroups take precedence0.086
G11C2013/0076Write operation performed depending on read result0.086
G11C2207/2263Write conditionally  e.g. only if new data and old data differ0.086
G06F2201/88Monitoring involving counting0.086
G06F11/34Recording or statistical evaluation of computer activity  e.g. of down time  of input/output operation | | Recording or statistical evaluation of user activity  e.g. usability assessment0.086
G11C2029/1204Bit line control0.086
G06F2212/1016Performance improvement0.086
G06F2201/81Threshold0.086
G06F2212/7208Multiple device management  e.g. distributing data over multiple flash devices0.085
G11C2211/5621Multilevel programming verification0.085
G11C2207/2245Memory devices with an internal cache buffer0.084
G11C2207/2254Calibration0.084
G11C2029/1806Address conversion or mapping  i.e. logical to physical address0.082
G11C2013/0092Write characterized by the shape  e.g. form  length  amplitude of the write pulse0.082
G11C2013/0066Verify correct writing whilst writing is in progress  e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing0.082
G11C2029/2602Concurrent test0.082
G11C2029/1206Location of test circuitry on chip or wafer0.082
G11C2029/3602Pattern generator0.082
G06F2212/7205Cleaning  compaction  garbage collection  erase control0.081
G06F2212/2022Flash memory0.081
H01L2224/16145the bodies being stacked0.081
H03M13/15Cyclic codes  i.e. cyclic shifts of codewords produce other codewords  e.g. codes defined by a generator polynomial  Bose-Chaudhuri-Hocquenghem [BCH] codes | (ref: H03M13/17)|  takes precedence0.081
G06F11/1428with loss of hardware functionality0.081
G11C2029/1202Word line control0.081
B41J2202/17Readable information on the head0.080
G11C2013/0085Write a page or sector of information simultaneously  e.g. a complete row or word line0.080
G11C2213/70Resistive array aspects0.080
G11C2216/04Nonvolatile memory cell provided with a separate control gate for erasing the cells  i.e. erase gate  independent of the normal read control gate0.079
G06F21/6245Protecting personal data  e.g. for financial or medical purposes0.079
G11C2213/79Array wherein the access device being a transistor0.078
G11C2213/82Array having  for accessing a cell  a word line  a bit line and a plate or source line receiving different potentials0.078
G11C2013/005Read using potential difference applied between cell electrodes0.078
G11C2013/0073Write using bi-directional cell biasing0.078
G06F2212/7203Temporary buffering  e.g. using volatile buffer or dedicated buffer blocks0.078
H04L7/027extracting the synchronising or clock signal from the received signal spectrum  e.g. by using a resonant or bandpass circuit0.078
G06F2009/45583Memory management  e.g. access or allocation0.077
G06F2221/2101Auditing as a secondary aspect0.077
G11C2207/2272Latency related aspects0.077
G11C2207/2281Timing of a read operation | sense amplifier timing | (ref: G11C7/06)|   | (ref: G11C7/08)0.077
G11C2207/229Timing of a write operation | sense amplifier timing | (ref: G11C7/06)|   | (ref: G11C7/08)0.077
G11C2211/5645Multilevel memory with current-mirror arrangements0.077
H01L2224/48225the item being non-metallic  e.g. insulating substrate with or without metallisation0.077
H01L2224/48227connecting the wire to a bond pad of the item0.077
H01L2224/33181On opposite sides of the body0.077
H01L2224/32225the item being non-metallic  e.g. insulating substrate with or without metallisation0.077
H01L2224/32145the bodies being stacked0.077
H01L2224/49175Parallel arrangements0.077
H01L2224/73215Layer and wire connectors0.077
H01L2224/73265Layer and wire connectors0.077
H01L2224/48106the connector being orthogonal to a side surface of the semiconductor or solid-state body  e.g. parallel layout0.077
H01L2224/29099Material0.077
H01L2224/32014the layer connector being smaller than the bonding area  e.g. bond pad0.077
H01L2224/06135Covering only the peripheral area of the surface to be connected  i.e. peripheral arrangements0.077
H01L2224/05599Material0.077
H01L2224/04042Bonding areas specifically adapted for wire connectors  e.g. wirebond pads0.077
H01L24/33of a plurality of layer connectors0.077
H01L2225/06506Wire or wire-like electrical connections between devices0.077
H01L2225/0651Wire or wire-like electrical connections from device to substrate0.077
H01L2225/06562at least one device in the stack being rotated or offset0.077
H01L2924/10161with a rectangular active surface0.077
H01L2225/06586Housing with external bump or bump-like connectors0.077
H01L2924/181Encapsulation0.077
H01L2924/00012Relevant to the scope of the group  the symbol of which is combined with the symbol of this group0.077
H01L2924/00014the subject-matter covered by the group  the symbol of which is combined with the symbol of this group  being disclosed without further technical details0.077
H01L2924/1434Memory0.077
H01L2224/45099Material0.077
H01L2224/48091Arched0.077
H04L25/0298Arrangement for terminating transmission lines0.076
H01L2924/15311being a ball array  e.g. BGA0.076
H01L2225/06589Thermal management  e.g. cooling0.076
H01L24/38of a plurality of strap connectors0.076
H01L2224/48145the bodies being stacked0.076
G11C2013/0054Read is performed on a reference element  e.g. cell  and the reference sensed value is used to compare the sensed value of the selected cell0.076
G11C2013/0042Read using differential sensing  e.g. bit line [BL] and bit line bar [BLB]0.076
G11C2013/0088Write with the simultaneous writing of a plurality of cells0.075
G06F2213/0056Use of address and non-data lines as data lines for specific data transfers to temporarily enlarge the data bus and increase information transfer rate0.075
B41J2002/14354Sensor in each pressure chamber0.075
G11C11/161details concerning the memory cell structure  e.g. the layers of the ferromagnetic memory cell0.075
G11C2211/5631Concurrent multilevel reading of more than one cell0.074
G11C2211/563Multilevel memory reading aspects0.074
G11C2211/5642Multilevel memory with buffers  latches  registers at input or output0.074
G11C2013/0057Read done in two steps  e.g. wherein the cell is read twice and one of the two read values serving as a reference value0.074
G09G2360/18Use of a frame buffer in a display terminal  inclusive of the display panel0.073
G09G2370/20Details of the management of multiple sources of image data0.073
G09G2340/0428Gradation resolution change0.073
G09G2330/12Test circuits or failure detection circuits included in a display system  as permanent part thereof0.073
G09G2320/029by monitoring one or more pixels in the display panel  e.g. by monitoring a fixed reference pixel0.073
G06F2212/7207management of metadata or control data0.073
G06F2212/7202Allocation control and policies0.073
H01L2224/08145the bodies being stacked0.072
G06F2212/1052Security improvement0.071
G06F2212/68Details of translation look-aside buffer [TLB]0.071
G11C11/5635Erasing circuits0.070
B41J2002/17586using ink bag deformation for ink level indication0.070
G06F2213/0016Inter-integrated circuit (I2C)0.070
G09G2310/04Partial updating of the display screen0.069
G09G2370/22Detection of presence or absence of input display information or of connection or disconnection of a corresponding information source0.069
G09G2380/10Automotive applications0.069
G09G2320/043Preventing or counteracting the effects of ageing0.069
G09G2320/041Temperature compensation0.069
Y02B20/40Control techniques providing energy savings  e.g. smart controller or presence detection0.069
B60Q2300/45Special conditions  e.g. pedestrians  road signs or potential dangers0.069
B60Q2300/42oncoming vehicle0.069
B60Q2300/054Variable non-standard intensity  i.e. emission of various beam intensities different from standard intensities  e.g. continuous or stepped transitions of intensity0.069
G09G2320/0693Calibration of display systems0.069
G09G2310/0286Details of a shift registers arranged for use in a driving circuit0.069
G09G2300/0819used for counteracting undesired variations  e.g. feedback or autozeroing0.069
G09G2310/08Details of timing specific for flat panels  other than clock recovery0.069
G11C2213/30Resistive cell  memory material aspects0.069
G11C2213/76Array using an access device for each cell which being not a transistor and not a diode0.069
G06F11/1443Transmit or communication errors0.069
H03M1/78using ladder network0.068
H03M1/46with digital/analogue converter for supplying reference values to converter0.068
G06F2212/7206Reconfiguration of flash memory system0.067
G11C2211/5644Multilevel memory comprising counting devices0.067
G06F2212/2532comprising a plurality of modules0.067
G11C2216/14Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory  typically a complete row or word line in flash memory0.067
G11C2211/5641Multilevel memory having cells with different number of storage levels0.067
H01L21/76805the opening being a via or contact hole penetrating the underlying conductor0.067
G09G2310/0264Details of driving circuits0.067
G09G2370/08Details of image data interface between the display device controller and the data line driver circuit0.067
G09G2320/064by time modulation of the brightness of the illumination source0.067
G02B2027/0132comprising binocular systems0.067
G09G2310/0267Details of drivers for scan electrodes  other than drivers for liquid crystal  plasma or OLED displays0.067
G09G2310/06Details of flat display driving waveforms0.067
G09G2310/0248Precharge or discharge of column electrodes before or after applying exact column voltages0.067
G09G2300/0814used for selection purposes  e.g. logical AND for partial update0.067
G02B2027/0178Eyeglass type  eyeglass details | (ref: G02C)0.067
G09G2320/0233Improving the luminance or brightness uniformity across the screen0.067
G02B2027/014comprising information/image processing systems0.067
H01L2224/02372connecting to a via connection in the semiconductor or solid-state body0.067
H01L2224/17181On opposite sides of the body0.067
H01L2224/17106the bump connectors being bonded to at least one common bonding area0.067
H01L2225/06513Bump or bump-like direct electrical connections between devices  e.g. flip-chip connection  solder bumps0.067
H01L2224/16227the bump connector connecting to a bond pad of the item0.067
H01L2224/16147the bump connector connecting to a bonding area disposed in a recess of the surface0.067
H01L2225/06517Bump or bump-like direct electrical connections from device to substrate0.067
H01L2224/16146the bump connector connecting to a via connection in the semiconductor or solid-state body0.067
H01L2225/06541Conductive via connections through the device  e.g. vertical interconnects  through silicon via [TSV] | manufacturing via connections | per se|  | (ref: H01L21/76898)0.067
H01L2225/06565the devices having the same size and there being no auxiliary carrier between the devices0.067
H01L2224/02375Top view0.067
H01L2224/02319by using a preform0.067
H01L24/13of an individual bump connector0.067
H01L2924/1432Central processing unit [CPU]0.067
H01L2924/1436Dynamic random-access memory [DRAM]0.067
H01L29/78with field effect produced by an insulated gate | (ref: H01L29/7725)|   | (ref: H01L29/775)|   | (ref: H01L29/778)|  take precedence0.066
G11C2207/108Wide data ports0.066
H04N5/3355with digital output of the sensor cell  e.g. dynamic RAM image sensors0.066
G09G2320/0646Modulation of illumination source brightness and image signal correlated to each other0.065
G09G2330/08Fault-tolerant or redundant circuits  or circuits in which repair of defects is prepared0.065
G09G2300/0857Static memory circuit  e.g. flip-flop0.065
G11C2029/0407on power on0.065
B01J2219/00659Two-dimensional arrays0.065
B01J2219/00653the compounds being bound to electrodes embedded in or on the solid supports0.065
B01J2219/00317Microwell devices  i.e. having large numbers of wells0.065
B01J2219/00713Electrochemical synthesis0.065
B01J2219/00722Nucleotides0.065
G11C2029/5602Interface to device under test0.065
G11C29/835with roll call arrangements for redundant substitutions0.065
G11C29/006at wafer scale level  i.e. wafer scale integration [WSI]0.065
G11C2029/4002Comparison of products  i.e. test results of chips or with golden chip0.065
G11C2029/1208Error catch memory0.065
H01L2224/16225the item being non-metallic  e.g. insulating substrate with or without metallisation0.065
H01L2924/014Solder alloys0.065
H01L2224/131with a principal constituent of the material being a metal or a metalloid  e.g. boron [B]  silicon [Si]  germanium [Ge]  arsenic [As]  antimony [Sb]  tellurium [Te] and polonium [Po]  and alloys thereof0.065
H01L27/0203Particular design considerations for integrated circuits0.065
G06F2212/3042being part of a memory device  e.g. cache DRAM0.065
G09G2330/021Power management  e.g. power saving0.065
G09G2300/0408Integration of the drivers onto the display substrate0.065
G11C2211/5648Multilevel memory programming  reading or erasing operations wherein the order or sequence of the operations is relevant0.065
G11C11/223using MOS with ferroelectric gate insulating film0.065
Y02T10/64Electric machine technologies in electromobility0.065
Y02T10/72Electric energy management in electromobility0.065
F16D2121/24using motors0.065
G11C2211/4013Memory devices with multiple cells per bit  e.g. twin-cells0.064
G06F2212/7209Validity control  e.g. using flags  time stamps or sequence numbers0.064
Y02E60/10Energy storage using batteries0.064
H01M2010/4271Battery management systems including electronic circuits  e.g. control of current or voltage to keep battery in healthy state  cell balancing0.064
G11C2213/75Array having a NAND structure comprising  for example  memory cells in series or memory elements in series  a memory element being a memory cell in parallel with an access transistor0.064
H01L45/124on sidewalls of dielectric structures  e.g. mesa or cup type devices0.064
H01L45/08based on migration or redistribution of ionic species  e.g. anions  vacancies0.064
Y02A90/10Information and communication technologies [ICT] supporting adaptation to climate change  e.g. for weather forecasting or climate simulation0.064
G11C2029/5006Current0.064
H01L2225/06596Structural arrangements for testing | testing or measuring during manufacture or treatment | (ref: H01L22/00)| | testing electrical properties or locating electrical faults | (ref: G01R31/00)0.064
H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by | (ref: H01L24/00)0.064
G06F2212/657Virtual address space management0.064
G11C2207/107Serial-parallel conversion of data or prefetch0.064
G11C2207/104Embedded memory devices  e.g. memories with a processing device on the same die or ASIC memory designs0.063
H01L2225/1047Details of electrical connections between containers0.063
H03F2200/537A transformer being used as coupling element between two amplifying stages0.063
H03F2200/451the amplifier being a radio frequency amplifier0.063
H03F2200/541Transformer coupled at the output of an amplifier0.063
F21W2102/13for high-beam region or low-beam region0.063
F21W2107/10for land vehicles0.063
G06F2212/1056Simplification0.063
G06F2212/214Solid state disk0.063
G06F2212/283Plural cache memories0.063
G06F2212/222Non-volatile memory0.063
G06F2221/2143Clearing memory  e.g. to prevent the data from being stolen0.063
H03K2005/00019Variable delay0.063
G09G2330/02Details of power systems and of start or stop of display operation0.063
G09G2310/0291Details of output amplifiers or buffers arranged for use in a driving circuit0.063
H04N9/04559based on four or more different wavelength filter elements0.062
H04N9/04555including elements transmitting or passing panchromatic light  e.g. white light0.062
H04L2209/34Encoding or coding  e.g. Huffman coding or error correction0.062
G11C2211/4016Memory devices with silicon-on-insulator cells0.062
H01L2224/48235connecting the wire to a via metallisation of the item0.062
H01L2924/3025Electromagnetic shielding0.062
H01L2224/8592Applying permanent coating  e.g. protective coating0.062
H01L2221/68345used as a support during the manufacture of self supporting substrates0.062
G11C2213/77Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used0.062
G11C2211/4062Parity or ECC in refresh operations0.062
H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]0.062
H01L2224/14181On opposite sides of the body0.062
H01L2224/0401Bonding areas specifically adapted for bump connectors  e.g. under bump metallisation [UBM]0.062
H01L2224/05552in top view0.062
H01L2224/13025the bump connector being disposed on a via connection of the semiconductor or solid-state body0.062
H01L2924/0002Not covered by any one of groups | (ref: H01L24/00)|   | (ref: H01L24/00)|  and | (ref: H01L2224/00)0.062
H01L2224/05571the external layer being disposed in a recess of the surface0.062
G06F2212/202Non-volatile memory0.062
G11C16/20Initialising| Data preset| Chip identification0.062
G06F2212/653Page colouring0.062
G06F2207/7219Countermeasures against side channel or fault attacks0.062
H03L7/06using a reference signal applied to a frequency- or phase-locked loop0.061
H03K2217/0081Power supply means  e.g. to the switch driver0.061
H04L41/34Signalling channels for network management communication0.061
H04L41/04Network management architectures or arrangements0.061
G11C2207/065Sense amplifier drivers0.061
G11C2029/5002Characteristic0.061
G09G2300/0465Improved aperture ratio  e.g. by size reduction of the pixel circuit  e.g. for improving the pixel density or the maximum displayable luminance or brightness0.061
G09G2320/0295by monitoring each display pixel0.061
G09G2310/061for resetting or blanking0.061
G09G2320/045Compensation of drifts in the characteristics of light emitting or modulating elements0.061
G09G2300/0426Layout of electrodes and connections0.061
G09G2300/08Active matrix structure  i.e. with use of active elements  inclusive of non-linear two terminal elements  in the pixels together with light emitting or modulating elements0.061
H01L2224/05569the external layer being disposed on a redistribution layer on the semiconductor or solid-state body0.060
H01L2224/05684Tungsten [W] as principal constituent0.060
H01L2224/05657Cobalt [Co] as principal constituent0.060
H01L2224/05647Copper [Cu] as principal constituent0.060
H01L2224/05624Aluminium [Al] as principal constituent0.060
H01L2924/047Silicides composed of metals from groups of the periodic table0.060
H01L2224/80001by connecting a bonding area directly to another bonding area  i.e. connectorless bonding  e.g. bumpless bonding0.060
H01L2224/80357being flush with the surface0.060
H01L2224/80895between electrically conductive surfaces  e.g. copper-copper direct bonding  surface activated bonding0.060
H01L2224/80896between electrically insulating surfaces  e.g. oxide or nitride layers0.060
H01L2224/94at wafer-level  i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices0.060
H01L2224/83896between electrically insulating surfaces  e.g. oxide or nitride layers0.060
H01L2224/83895between electrically conductive surfaces  e.g. copper-copper direct bonding  surface activated bonding0.060
H01L2224/1703Bump connectors having different sizes  e.g. different diameters  heights or widths0.060
H01Q1/24with receiving set0.060
H01L2225/06568the devices decreasing in size  e.g. pyramidical stack0.060
H01L2225/04the devices not having separate containers0.060
H01L2224/13111Tin [Sn] as principal constituent0.060
H01L2224/13139Silver [Ag] as principal constituent0.060
H01L2223/6677for antenna  e.g. antenna included within housing of semiconductor device | antennas | per se|  | (ref: H01Q)0.060
H01L2224/13147Copper [Cu] as principal constituent0.060
G06N3/0427in combination with an expert system0.060
G06F3/0446using a grid-like structure of electrodes in at least two directions  e.g. using row and column electrodes0.060
G06F3/0416Control or interface arrangements specially adapted for digitisers0.060
G11C2207/068Integrator type sense amplifier0.060
G06T2200/32involving image mosaicing0.060
G06T2200/28involving image processing hardware0.060
G06T2200/00Indexing scheme for image data processing or generation  in general0.060
H03M1/76using switching tree0.060
H03M1/361having a separate comparator and reference value for each quantisation level  i.e. full flash converter type0.060
G09G2300/026Video wall  i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions0.060
G09G2330/10Dealing with defective pixels0.060
G09G2300/0804Sub-multiplexed active matrix panel  i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements0.060
G09G2300/0842forming a memory circuit  e.g. a dynamic memory with one capacitor0.060
G09G2320/0626for control of overall brightness0.060
G09G2300/0861with additional control of the display period without amending the charge stored in a pixel memory  e.g. by means of additional select electrodes0.060
G09G2310/0221with use of split matrices | (ref: G09G3/3644)|  and | (ref: G09G3/3666)|  take precedence0.060
G06F2212/221Static RAM0.060
G06F2212/656Address space sharing0.060
G11C2211/406Refreshing of dynamic cells0.060
G09G2310/0202Addressing of scan or signal lines0.060
H01L27/11509characterised by the peripheral circuit region0.060
H01L21/31144using masks0.060
H01L21/31111by chemical means0.060
H01L21/0274Photolithographic processes0.060
G11C2029/5004Voltage0.060
H01L2224/45139Silver (Ag) as principal constituent0.060
H01L2224/45124Aluminium (Al) as principal constituent0.060
H01L2224/45147Copper (Cu) as principal constituent0.060
H01L2225/06524Electrical connections formed on device or on substrate  e.g. a deposited or grown layer0.060
H01L2224/48463the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond0.060
H01L24/45of an individual wire connector0.060
H01L2224/4847the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond0.060
H01L2224/95at chip-level  i.e. with connecting carried out on a plurality of singulated devices  i.e. on diced chips0.060
H01L2224/82by forming build-up interconnects at chip-level  e.g. for high density interconnects [HDI]0.060
H01L2224/45144Gold (Au) as principal constituent0.060
H01L2224/08148the bonding area connecting to a bonding area protruding from the surface of the body0.060
G06F11/1056Updating check bits on partial write  i.e. read/modify/write0.060
H03B2200/0074Locking of an oscillator by injecting an input signal directly into the oscillator0.059
A61N1/0529Electrodes for brain stimulation0.059
H03B2200/0076Power combination of several oscillators oscillating at the same frequency0.059
A61B5/0006ECG or EEG signals0.059
A61B5/4836Diagnosis combined with treatment in closed-loop systems or methods | (ref: A61B5/0036)|  takes precedence0.059
H01L2924/3011Impedance0.059
G06F12/145the protection being virtual  e.g. for virtual blocks or segments before a translation mechanism0.059
G11C2213/15Current-voltage curve0.059
G11C2029/3202Scan chain0.059
G06F2212/6024History based prefetching0.059
G06F2209/501Performance criteria0.058
G06F2221/034Test or assess a computer or a system0.058
G09G2330/06Handling electromagnetic interferences [EMI]  covering emitted as well as received electromagnetic radiation0.058
G09G2300/0421Structural details of the set of electrodes0.058
G11C2207/063Current sense amplifiers0.058
G11C13/00Digital stores characterised by the use of storage elements not covered by groups | (ref: G11C11/00)|   | (ref: G11C23/00)|   or | (ref: G11C25/00)0.058
G11C2013/0052Read process characterized by the shape  e.g. form  length  amplitude of the read pulse0.058
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