Validity Report
Basic Report
US7057960B1 — Method and architecture for reducing the power consumption for memory devices in refresh operations
Priority Date: 2002-03-04, Publication Date: 2006-06-06, Current Assignee: Innomemory LLCReport Generated: 2022-07-26
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Patent Id
Score
Title
Patent Type
Publication Date
Priority Date
Search Efficiency
Original Assignee
Current Assignee
EP0685851B1●●●●●Control circuitry for shared data bus in a memory integrated circuitGRANT1999-12-011994-05-31GreatSTMicroelectronics lnc USA, SGS Thomson Microelectronics IncSTMicroelectronics lnc USA
EP1049104A1●●●●●Technique for testing bitline and related circuitry of a memory arrayGRANT2000-11-021999-04-30GreatSTMicroelectronics lnc USASTMicroelectronics lnc USA
EP0465808B1●●●●●Variable size set associative DRAM redundancy schemeGRANT1998-07-291990-06-19GreatTexas Instruments IncTexas Instruments Inc
EP1049103A1●●●●●Techniue for testing wordline and related circuitry of a memory arrayGRANT2000-11-021999-04-30GreatSTMicroelectronics lnc USASTMicroelectronics lnc USA
EP1282133A1●●●●●SEMICONDUCTOR MEMORYGRANT2003-02-052000-03-08GreatNEC CorpNEC Electronics Corp
EP0820065A2●●●●●Dynamic memory device with refresh circuit and refresh methodGRANT1998-01-211996-07-15GreatMotorola IncMotorola Solutions Inc
EP1315176B1●●●●●Memory circuit having parity cell arrayGRANT2009-10-212001-11-22GreatFujitsu Semiconductor LtdFujitsu Semiconductor Ltd
EP0239916A2●●●●●Semiconductor memory device having a test mode and a standard mode of operationGRANT1987-10-071986-03-24GreatNEC CorpNEC Corp
EP0017862A1●●●●●Memory deviceGRANT1980-10-291979-04-04GreatNEC CorpNEC Corp
US6469947B2●●●●●Semiconductor memory device having regions with independent word lines alternately selected for refresh operationGRANT2002-10-221999-06-29GreatHyundai Electronics Co LtdSK Hynix Inc
EP0060250A1●●●●●CLOCKING SYSTEM FOR A SELF-REFRESHED DYNAMIC MEMORYGRANT1982-09-221980-09-10GreatMostek CorpCTU of Delaware Inc
US6166980A●●●●●Refresh controller in semiconductor memoryGRANT2000-12-261998-10-28GreatHyundai Electronics Industries Co LtdSK Hynix Inc
EP0469571B1●●●●●Redundant semiconductor memory deviceGRANT1997-11-121990-07-31GreatTexas Instruments IncTexas Instruments Inc
US4079462A●●●●●Refreshing apparatus for MOS dynamic RAMsGRANT1978-03-141976-05-07GreatIntel CorpIntel Corp
US6560155B1●●●●●System and method for power saving memory refresh for dynamic random access memory devices after an extended intervalGRANT2003-05-062001-10-24GreatMicron Technology IncMicron Technology Inc
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Predictive Analytics

Composite Research Score (1-10)
9
  HARD
Art VolumeMEDIUM
Tech ComplexityINTRICATE
Priority DateEARLY
Tech DiversityBROAD
Expert Services Estimate$4,950 — $5,400
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Possible Classes
1,405
Recommended Classes
352
Government Assigned Classes
1
CPC
Title
Score
G11C11/406Management or control of the refreshing or charge-regeneration cycles●●●●●
G11C11/40618Refresh operations over multiple banks or interleaving●●●●●
G11C11/40611External triggering or timing of internal or partially internal refresh operations  e.g. auto-refresh or CAS-before-RAS triggered refresh●●●●●
G11C11/4085Word line control circuits  e.g. word line drivers  - boosters  - pull-up  - pull-down  - precharge●●●●●
G11C8/10Decoders●●●●●
G11C11/40615Internal triggering or timing of refresh  e.g. hidden refresh  self refresh  pseudo-SRAMs●●●●●
G11C29/76using address translation or modifications●●●●●
G11C29/4401for self repair●●●●●
G11C7/1006Data managing  e.g. manipulating data before writing or reading out  data bus switches or control circuits therefor●●●●●
G11C11/2275Writing or programming circuits or methods●●●●●
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