Digital Logic Design Lab (EENG 2890-003)

Fall-2017

_______________________________________________________________________________________

Instructor: Parthasarathy (Partha) Guturu            
Faculty Office: NTDP B-235
Phone: 940-891-6877
Email: guturu@unt.edu
Teaching Assistant: Puja Sah
Class Hours: W 5:30 PM - 8:20 PM
Class Room: NTDP B-207
Office Hours: Tuesday 3:30 PM-4:30 PM. Students unable to see me during these times may request an appointment.

Reference Book

1. Digital Logic Circuit Analysis & Design, 1st Ed. V. P. Nelson, H. T. Nagle, J. D. Irwin, and B. D. Carroll, Prentice Hall, 1995. ISBN: 0-13-463894-8.

Attendance Policy:     In view of the continuous evaluation strategy adopted by the instructor, perfect attendance is recommended for those aspiring to get good grades.

Grading Policy:          Grades are decided by the experimental demos and lab reports.

Academic Dishonesty: Honesty is the best policy. Cheating will not be tolerated. Anyone found guilty of cheating on a test or assignment will be awarded an F grade for the course. Discussions of problems and assignment with your classmates is welcome and encouraged, however, sharing of solutions is not. If you need help, you should ask the instructor. Cheating includes, but is not limited to, all forms of plagiarism and misrepresentation. For your rights and responsibilities please refer to http://www.unt.edu/csrr

Statement regarding Disabled Students: The Faculty of Electrical Engineering including this instructor cooperates with the Office of Disability Accommodation (ODA) to make reasonable accommodations for students with certified disabilities (cf. Americans with Disabilities Act and Section 504, Rehabilitation Act). If you have not registered with ODA, we encourage you to do so immediately and present a written accommodation request along with an appropriate documentation from the Dean of Students Office http://www.unt.edu/oda/, on or before the 2nd week of class.

Final Exam Date and Time: TBD.

List of Experiments

1.      Three configurations of EX-OR

i)                    Using AND, OR, NOT gates (2 NOT gates, 1 AND gate, and 1 OR gate)

ii)                  Using NAND (Universal) gates only (5 NAND gates are required)

iii)                Using NOR (Universal) gates only (5 NOR gates are required)

2.      K- Map minimization of a 4 variable Boolean function

Students are required to implement the original circuit, and the two minimal (SOP and POS) circuits and verify that the truth tables in all the three cases are the same. The original implementation of canonical form requires 4 NOT gates, 8 4-input AND gates (or equivalently 24 2-input AND gates), 2 4-input OR gates plus 1 2-input OR-gates (or equivalently 7 2 input OR gates). SOP minimal circuit requires 4 NOT gates,   4 3-input AND gates (equivalently 8 2-input AND gates), 1 4-input OR gate (or 3 2-input OR gates). POS minimal circuit requires 4 NOT gates,   4 3-input OR gates (equivalently 8 2-input OR gates), 1 4-input AND gate (or 3 2-input AND gates).

3.      4 to 16  matrix decoder using 16 AND gates

4.      8 to 3 parity encoder

5.      7 segment display using 4 to 16 decoder, 7 LEDs, and  AND gates.

6.      4 2-bit word multiplexer

7.      Demultiplexer  to distribute 2-bit word to 4 destinations

8.      4 bit shift register

9.      BCD counter (both synchronous and asynchronous modes) using 4 JK flipflops and basic gates

10.  16x4 memory

 

Reading Requirements: The students are required to come prepared to every class with the material discussed in the previous class.

Course Learning Outcomes (CLOs)

Course Learning Outcomes (CLOs), that is, the areas for student learning in this course are:

[CLO-1]                   Digital and Analog Systems: Basic Concepts and Historical Perspective

[CLO-2]                   Importance of Learning to Learn (L2L) and Project-Based Learning (PBL) in learning Digital Logic Design.

[CLO-3]                   Number Systems and Digital Logic Gates

[CLO-4]                   Boolean Algebra, Switching Functions and Canonical Forms

[CLO-5]                   Combinational Circuit Minimization, Analysis, and Synthesis

[CLO-6]                   Sequential circuits elements and sequential logic circuits

[CLO-7]                   Modular Sequential Logic- Counters and shift registers

[CLO-8]                   Minimal Design of Synchronous Sequential Circuits

[CLO-9]                   Digital Logic Testing

[CLO-10]               Lab Report Writing

Student Outcomes (SOs)of Our BSEE Program

Upon completion of our BSEE program, the students will be able to:

[SO-1] An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics.

 

[SO-2] An ability to apply the engineering design process to produce solutions that meet

specified needs with consideration for public health and safety, and global, cultural, social, environmental, economic, and other factors as appropriate to the Electrical Engineering discipline.

 

 [SO-3] An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions.

 

[SO-4] An ability to communicate effectively with a range of audiences.

 

[SO-5] An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts.

 

[SO-6] An ability to recognize the ongoing need to acquire new knowledge, to choose appropriate learning strategies, and to apply this knowledge.

 

[SO-7] An ability to function effectively as a member or leader of a team that establishes goals, plans tasks, meets deadlines, and creates a collaborative and inclusive environment.

 

ABET Criterion 3 Outcomes

[1].                        An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics.

[2].                        An ability to apply the engineering design process to produce solutions that meet specified needs with consideration for public health and safety, and global, cultural, social, environmental, economic, and other factors as appropriate to the discipline.

[3].                        An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions.

[4].                        An ability to communicate effectively with a range of audiences.

[5].                        An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts.

[6].                        An ability to recognize the ongoing need to acquire new knowledge, to choose appropriate learning strategies, and to apply this knowledge.

[7].                        An ability to function effectively as a member or leader of a team that establishes goals, plans tasks, meets deadlines, and creates a collaborative and inclusive environment.

Relationship between the Course Learning Outcomes and Student/ABET Outcomes

The course learning outcomes map onto the program and ABET outcomes as depicted in the table below.

 

CLO

Student/ABET Criterion 3 Outcomes

 

SO-1/ 3 [1]

SO-2/ 3 [2]

SO-3/ 3 [3]

SO-4/ 3 [4]

SO-5/ 3 [5]

SO-6/ 3 [6]

SO-7/

3 [7]

1

 

 

 

 

 

2

 

 

 

 

x

 

3

x

 

 

 

 

 

4

x

 

 

 

 

 

5

x

 

 

 

 

 

6

x

 

 

 

 

 

7

x

 

 

 

 

 

 

8

x

 

 

 

 

 

9

x

 

 

 

10

 

 

x