Digital Logic
Design (EENG 2710-002)
Spring-2020
_______________________________________________________________________________________
Instructor: Parthasarathy
(Partha)
Guturu
Faculty Office: NTDP B-235
Phone: 940-891-6877
Email: Parthasarathy.Guturu@unt.edu (also pg0028@unt.edu )
Teaching Assistant: Vinitha Pingili
Class Hours: Tue/Th. 2:30 PM -
3:50 PM
Class Room: NTDP B-155
Office Hours: Wednesday 12:00 PM-1:00
PM. Students unable to see me during these times may request an appointment.
Reference Book
1. Digital Logic Circuit Analysis & Design, 1st
Ed. V. P. Nelson, H. T. Nagle, J. D. Irwin, and B. D. Carroll, Prentice Hall,
1995. ISBN: 0-13-463894-8.
References
1. DSCH freeware from www.microwind.org for executing a Digital Design Project.
2. A power-point
presentation is uploaded on
canvas, but it should not be considered as a substitute for class notes as it provides
only some information to support and supplement a student-centric
problem/project-oriented learning methodology.
3. Good documentation is
an essential component of a successful project. I will discuss in the class how
to write the project report, and provide a sample report on canvas.
Attendance Policy: In view of the continuous evaluation
strategy adopted by the instructor, perfect attendance is recommended for those
aspiring to get good grades.
Grading Policy:
Assignments/Quizzes/Class
Tests: 60%, Project: 25%, and Final Assignment: 15%. Grades A, B, C, D, and F
will be assigned, respectively,
depending upon whether the total tally will be greater than/equal to 90,
80-89, 70-79, 60-69, or less than 60.
However, this mapping of marks to grades may vary depending upon the class
performance in general.
Academic Dishonesty: Honesty is the best policy. Cheating will not be tolerated. Anyone found guilty of cheating on a
test or assignment will be awarded an F grade for the course. Discussions of
problems and assignment with your classmates is welcome and encouraged,
however, sharing of solutions is not. If you need help, you should ask the
instructor. Cheating includes, but is not limited to, all forms of plagiarism
and misrepresentation. For your rights and responsibilities please refer to http://www.unt.edu/csrr
Statement regarding
Disabled Students: The Faculty of Electrical Engineering
including this instructor cooperates with the Office of Disability
Accommodation (ODA) to make reasonable accommodations for students with
certified disabilities (cf. Americans with Disabilities Act and Section 504,
Rehabilitation Act). If you have not registered with ODA, we encourage you to
do so immediately and present a written accommodation request along with an
appropriate documentation from the Dean of Students Office http://www.unt.edu/oda/, on or before the 2nd week of
class.
Final Exam Date and Time:
TBD.
Course
Outline and Delivery Plan
|
Topic No. |
Topic |
Time Allocated |
|
1. |
Digital
and analog systems- an introduction, historical perspective, importance of
L2L and PBL |
1 Week |
|
2. |
Number
systems and codes |
1 Week |
|
3. |
Boolean
Algebra, Switching functions and canonical forms |
2 Weeks |
|
4. |
Circuit
minimization, Analysis of combinational circuits, and Timing issues |
1.5 Weeks |
|
5. |
Top-down
Modular Design of Combinational Logic |
1.5 Weeks |
|
6. |
Sequential
Circuit Elements- Latches and flip-flops |
1 Week |
|
7. |
Modular
Sequential Logic- Counters and shift registers |
2 Weeks |
|
8. |
Analysis
and Design of synchronous sequential circuits |
3 Weeks |
|
9. |
Analysis
and Design of asynchronous sequential circuits |
1 Week |
|
10. |
Digital
Logic Testing |
1 Week |
Reading Requirements: The
students are required to come prepared to every class with the material
discussed in the previous class.
Course Learning
Outcomes (CLOs)
Course Learning Outcomes (CLOs), that is, the areas for student learning in this course are:
[CLO-1] Digital and Analog Systems: Basic Concepts and Historical Perspective
[CLO-2] Importance of Learning to Learn (L2L) and Project-Based Learning (PBL) in learning Digital Logic Design.
[CLO-3] Number Systems, Digital Logic Gates, and Boolean algebra
[CLO-4] Switching Functions, Canonical Forms, and Minimization
[CLO-5] Combinational Circuit Analysis, and Synthesis (Design)
[CLO-6] Sequential circuits elements(latches and flip-flops) and sequential logic circuits
[CLO-7] Finite State Machine Modeling and Modular Sequential Logic- Counters and shift registers
[CLO-8] Analysis and Minimal Design of Synchronous Sequential Circuits
[CLO-9] Analysis and Design of asynchronous sequential circuits
[CLO-10] Digital Logic Testing
[CLO-11] Team Project Execution
[CLO-12] Project Report Writing
Our EE Program Student Outcomes (SOs) (and ABET
Criterion 3 Outcomes)
Upon completion of our BSEE
program, the students will be able to:
[SO-1/ABET 3-1] identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics,
[SO-2/ABET 3-2] apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors,
[SO-3/ABET 3-3] communicate effectively with a range of audiences,
[SO-4/ ABET 3-4] recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts,
[SO-5/ABET 3-5] function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives,
[SO-6/ABET 3-6] develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions, and
[SO-7/ABET 3-7] acquire and apply new knowledge as needed, using appropriate learning strategies.
Relationship between
Our BSEE Program Student Outcomes and Course Learning Outcomes
The course learning
outcomes map onto our program’s student outcomes and ABET outcomes as depicted
in the table below:
|
CLO |
Student Outcomes/ABET Outcomes |
|
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|
SO-1 |
SO-2 |
SO-3 |
SO-4 |
SO-5 |
SO-6 |
SO-7 |
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1 |
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x |
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2 |
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x |
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3 |
x |
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4 |
x |
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5 |
x |
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6 |
x |
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7 |
x |
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8 |
x |
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9 |
x |
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10 |
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|
x |
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11 |
x |
x |
x |
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12 |
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x |
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