Digital Logic
Design (EENG 2710-001)
Fall-2017
Homework-1 (Due before Class Time on
09/18/2017 (Monday))
Homework-2 (Due after Class Time on 10/02/2017
(Monday))
Homework-3 (Due before
Class Time on 10/25/2017 (Wednesday))
Homework-4 (Due after
Class Time on 11/20/2017 (Monday))
Homework-5 (Due after Class Time on 12/04/2017 (Monday))
PROJECT
(Due on 12/06/2017 (Wednesday))
______________________________________________________________________
Instructor: Parthasarathy
(Partha)
Guturu
Faculty Office: NTDP B-235
Phone: 940-891-6877
Email: guturu@unt.edu
Teaching Assistant: Anirban Chakraborty
Class Hours: M/W 10:00 AM - 11:20
AM
Class Room: NTDP B-242
Office Hours: Tuesday 3:30 PM-4:30 PM. Students
unable to see me during these times may request an appointment.
Reference Book
1. Digital Logic Circuit Analysis & Design, 1st
Ed. V. P. Nelson, H. T. Nagle, J. D. Irwin, and B. D. Carroll, Prentice Hall,
1995. ISBN: 0-13-463894-8.
References
1. DSCH freeware from www.microwind.org for executing a Digital Design Project
2. A power-point presentation is
used to provide some information to support and supplement a student-centric
problem/project-oriented learning methodology.
3. Good documentation is
an essential component of a successful project. Please see the following report
(in PDF) on how to write project reports.
Attendance Policy: In view of the continuous evaluation
strategy adopted by the instructor, perfect attendance is recommended for those
aspiring to get good grades.
Grading Policy:
Assignments/Quizzes/Class
Tests: 60%, Project: 25%, and Final Examination: 15%. Grades A, B, C, D, and F
will be assigned, respectively,
depending upon whether the total tally will be greater than/equal to 90,
80-89, 70-79, 60-69, or less than 60.
However, this mapping of marks to grades may vary depending upon the class
performance in general.
Academic Dishonesty: Honesty is the best policy. Cheating will not be tolerated. Anyone found guilty of cheating on a
test or assignment will be awarded an F grade for the course. Discussions of
problems and assignment with your classmates is welcome and encouraged,
however, sharing of solutions is not. If you need help, you should ask the
instructor. Cheating includes, but is not limited to, all forms of plagiarism
and misrepresentation. For your rights and responsibilities please refer to http://www.unt.edu/csrr
Statement regarding
Disabled Students: The Faculty of Electrical Engineering
including this instructor cooperates with the Office of Disability
Accommodation (ODA) to make reasonable accommodations for students with
certified disabilities (cf. Americans with Disabilities Act and Section 504,
Rehabilitation Act). If you have not registered with ODA, we encourage you to
do so immediately and present a written accommodation request along with an
appropriate documentation from the Dean of Students Office http://www.unt.edu/oda/, on or before the 2nd week of
class.
Final Exam Date and Time:
TBD.
Course
Outline and Delivery Plan
|
Topic No. |
Topic |
Time Allocated |
|
1. |
Digital
and analog systems- an introduction, historical perspective, importance of
L2L and PBL |
1 Week |
|
2. |
Number
systems and codes |
1 Week |
|
3. |
Boolean
Algebra, Switching functions and canonical forms |
2 Weeks |
|
4. |
Circuit
minimization, Analysis of combinational circuits, and Timing issues |
1.5 Weeks |
|
5. |
Top-down
Modular Design of Combinational Logic |
1.5 Weeks |
|
6. |
Sequential
Circuit Elements- Latches and flip-flops |
1 Week |
|
7. |
Modular
Sequential Logic- Counters and shift registers |
2 Weeks |
|
8. |
Analysis
and Design of synchronous sequential circuits |
3 Weeks |
|
9. |
Analysis
and Design of asynchronous sequential circuits |
1 Week |
|
10. |
Digital
Logic Testing |
1 Week |
Reading Requirements: The
students are required to come prepared to every class with the material
discussed in the previous class.
Course Learning
Outcomes (CLOs)
Course Learning Outcomes (CLOs), that is, the areas for student learning in this course are:
[CLO-1] Digital and Analog Systems: Basic Concepts and Historical Perspective
[CLO-2] Importance of Learning to Learn (L2L) and Project-Based Learning (PBL) in learning Digital Logic Design.
[CLO-3] Number Systems and Digital Logic Gates
[CLO-4] Boolean Algebra, Switching Functions and Canonical Forms
[CLO-5] Combinational Circuit Minimization, Analysis, and Synthesis
[CLO-6] Sequential circuits elements and sequential logic circuits
[CLO-7] Modular Sequential Logic- Counters and shift registers
[CLO-8] Minimal Design of Synchronous Sequential Circuits
[CLO-9] Analysis and Design of asynchronous sequential circuits
[CLO-10] Digital Logic Testing
[CLO-11] Project-based Learning (PBL) - Digital Project execution from requirements through design and testing
[CLO-12] Project Report Writing
Student Outcomes (SOs)of Our
BSEE Program
Upon completion of our BSEE
program, the students will be able to:
[SO-1] An
ability to identify, formulate, and solve complex engineering problems by
applying principles of engineering, science, and mathematics.
[SO-2] An
ability to apply the engineering design process to produce solutions that meet
specified
needs with consideration for public health and safety, and global, cultural,
social, environmental, economic, and other factors as appropriate to the
Electrical Engineering discipline.
[SO-3] An ability to
develop and conduct appropriate experimentation, analyze and interpret data,
and use engineering judgment to draw conclusions.
[SO-4] An
ability to communicate effectively with a range of audiences.
[SO-5] An
ability to recognize ethical and professional responsibilities in engineering
situations and make informed judgments, which must consider the impact of
engineering solutions in global, economic, environmental, and societal
contexts.
[SO-6] An
ability to recognize the ongoing need to acquire new knowledge, to choose
appropriate learning strategies, and to apply this knowledge.
[SO-7] An
ability to function effectively as a member or leader of a team that
establishes goals, plans tasks, meets deadlines, and creates a collaborative
and inclusive environment.
ABET Criterion 3 Outcomes
[1].
An ability to identify, formulate, and
solve complex engineering problems by applying principles of engineering,
science, and mathematics.
[2].
An ability to apply the engineering design
process to produce solutions that meet specified needs with consideration for
public health and safety, and global, cultural, social, environmental,
economic, and other factors as appropriate to the discipline.
[3].
An ability to develop and conduct
appropriate experimentation, analyze and interpret data, and use engineering
judgment to draw conclusions.
[4].
An ability to communicate effectively with
a range of audiences.
[5].
An ability to recognize ethical and
professional responsibilities in engineering situations and make informed
judgments, which must consider the impact of engineering solutions in global,
economic, environmental, and societal contexts.
[6].
An ability to recognize the ongoing need to
acquire new knowledge, to choose appropriate learning strategies, and to apply
this knowledge.
[7].
An ability to function effectively as a
member or leader of a team that establishes goals, plans tasks, meets
deadlines, and creates a collaborative and inclusive environment.
Relationship between
the Course Learning Outcomes and Student/ABET Outcomes
The course learning outcomes map onto the program and ABET outcomes as
depicted in the table below.
|
CLO |
Student/ABET Criterion 3 Outcomes |
||||||
|
|
SO-1/ 3 [1] |
SO-2/ 3 [2] |
SO-3/ 3 [3] |
SO-4/ 3 [4] |
SO-5/ 3 [5] |
SO-6/ 3 [6] |
SO-7/ 3 [7] |
|
1 |
|
|
|
|
|
||
|
2 |
|
|
|
|
x |
|
|
|
3 |
x |
|
|
|
|
|
|
|
4 |
x |
|
|
|
|
|
|
|
5 |
x |
|
|
|
|
|
|
|
6 |
x |
|
|
|
|
|
|
|
7 |
x |
|
|
|
|
|
|
|
8 |
x |
|
|
|
|
|
|
|
9 |
x |
|
|
|
|
|
|
|
10 |
x |
|
|
|
|||
|
11 |
x |
x |
|
|
|
||
|
12 |
|
|
x |
|
|
||