Digital Logic
Design (EENG 2710-002)
Spring-2017
_______________________________________________________________________________________
Instructor: Parthasarathy
(Partha) Guturu
Faculty Office: NTDP B-235
Phone: 940-891-6877
Email: guturu@unt.edu
Teaching Assistant: TBD
Class Hours: Tue/Th
10:00 AM - 11:20 AM
Class Room: NTDP B-242
Office Hours: Monday 3:0 0 AM-4:00 PM. Students
unable to see me during these times may request an appointment.
Reference Book
1. Digital Logic Circuit Analysis & Design, 1st
Ed. V. P. Nelson, H. T. Nagle, J. D. Irwin, and B. D. Carroll, Prentice Hall, 1995.
ISBN: 0-13-463894-8.
References
1. DSCH freeware from www.microwind.org for executing a Digital Design Project
2. A power-point presentation is
used to provide some information to support and supplement a student-centric
problem/project-oriented learning methodology.
3. Good documentation is
an essential component of a successful project. Please see the following report
(in PDF) on how to write project reports.
Attendance Policy: In view of the continuous evaluation
strategy adopted by the instructor, perfect attendance is recommended for those
aspiring to get good grades.
Grading Policy:
Assignments/Quizzes/Class
Tests: 60%, Project: 25%, and Final Examination: 15%. Grades A, B, C, D, and F
will be assigned, respectively,
depending upon whether the total tally will be greater than/equal to 90,
80-89, 70-79, 60-69, or less than 60.
However, this mapping of marks to grades may vary depending upon the class
performance in general.
Academic Dishonesty: Honesty is the best policy. Cheating will not be tolerated. Anyone found guilty of cheating on a
test or assignment will be awarded an F grade for the course. Discussions of
problems and assignment with your classmates is welcome and encouraged,
however, sharing of solutions is not. If you need help, you should ask the
instructor. Cheating includes, but is not limited to, all forms of plagiarism
and misrepresentation. For your rights and responsibilities please refer to http://www.unt.edu/csrr
Statement regarding
Disabled Students: The Faculty of Electrical Engineering
including this instructor cooperates with the Office of Disability
Accommodation (ODA) to make reasonable accommodations for students with
certified disabilities (cf. Americans with Disabilities Act and Section 504,
Rehabilitation Act). If you have not registered with ODA, we encourage you to
do so immediately and present a written accommodation request along with an
appropriate documentation from the Dean of Students Office http://www.unt.edu/oda/, on or before the 2nd week of
class.
Final Exam Date and Time:
TBD.
Course
Outline and Delivery Plan
|
Topic No. |
Topic |
Time Allocated |
|
1. |
Digital
and analog systems- an introduction, historical perspective, importance of
L2L and PBL |
1 Week |
|
2. |
Number
systems and codes |
1 Week |
|
3. |
Boolean
Algebra, Switching functions and canonical forms |
2 Weeks |
|
4. |
Circuit
minimization, Analysis of combinational circuits, and Timing issues |
1.5 Weeks |
|
5. |
Top-down
Modular Design of Combinational Logic |
1.5 Weeks |
|
6. |
Sequential
Circuit Elements- Latches and flip-flops |
1 Week |
|
7. |
Modular
Sequential Logic- Counters and shift registers |
2 Weeks |
|
8. |
Analysis
and Design of synchronous sequential circuits |
3 Weeks |
|
9. |
Analysis
and Design of asynchronous sequential circuits |
1 Week |
|
10. |
Digital
Logic Testing |
1 Week |
Reading Requirements: The
students are required to come prepared to every class with the material
discussed in the previous class.
Course Learning
Outcomes (CLOs)
Course Learning Outcomes (CLOs), that is, the areas for student learning in this course are:
[CLO-1] Digital and Analog Systems: Basic Concepts and Historical Perspective
[CLO-2] Importance of Learning to Learn (L2L) and Project-Based Learning (PBL) in learning Digital Logic Design.
[CLO-3] Number Systems and Digital Logic Gates
[CLO-4] Boolean Algebra, Switching Functions and Canonical Forms
[CLO-5] Combinational Circuit Minimization, Analysis, and Synthesis
[CLO-6] Sequential circuits elements and sequential logic circuits
[CLO-7] Modular Sequential Logic- Counters and shift registers
[CLO-8] Minimal Design of Synchronous Sequential Circuits
[CLO-9] Analysis and Design of asynchronous sequential circuits
[CLO-10] Digital Logic Testing
[CLO-11] Project-based Learning (PBL) - Digital Project execution from requirements through design and testing
[CLO-12] Project Report Writing
Student Outcomes (SOs)of Our
BSEE Program
Upon completion of our BSEE
program, the students will be able to:
[SO-1] Apply knowledge of mathematics, engineering and science.
[SO-2] Design and conduct experiments to verify and validate the design projects developed by them, and analyze and interpret data.
[SO-3] Develop project-based learning skills through design and implementation of a system, component, or process that meets the needs within realistic constraints.
[SO-4] Function on multidisciplinary teams.
[SO-5] Identify, formulate, and solve engineering problems.
[SO-6] Have an understanding of professional and ethical responsibility.
[SO-7] Communicate effectively.
[SO-8] Achieve broad education necessary to understand the impact of electrical engineering solutions in a global and societal context.
[SO-9] Understand learning
processes, concepts of learning to learn, and engage in lifelong learning.
[SO-10] Achieve knowledge of contemporary issues.
[SO-11] Use techniques, skills, and computer-based tools for conducting experiments and carrying out designs.
ABET Outcomes
3a- an ability to apply knowledge of mathematics, science, and engineering
3b- an ability to design and conduct experiments, as well as to analyze and interpret data
3c- an ability to design a system, component, or process to meet desired needs
3d- an ability to function on multi-disciplinary teams
3e- an ability to identify, formulate, and solve engineering problems
3f- an understanding of professional and ethical responsibility
3g- an ability to communicate effectively
3h- the broad education necessary to understand the impact of engineering solutions in a global and societal context
3i- a recognition of the need for, and an ability to engage in life-long learning
3j- a knowledge of contemporary issues
3k- an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice
Relationship between
the Course Learning Outcomes and Student/ABET Outcomes
The course learning
outcomes map onto the program and ABET outcomes as depicted in the table below.
|
CLO |
Student Outcomes/ABET Outcomes |
||||||||||
|
|
SO-1/ 3(a) |
SO-2/ 3(b) |
SO-3/ 3(c) |
SO-4/ 3(d) |
SO-5/ 3(e) |
SO-6/ 3(f) |
SO-7/ 3(g) |
SO-8/ 3(h) |
SO-9/ 3(i) |
SO-10/ 3(j) |
SO-11/ 3(k) |
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