WEBVTT NOTE Digital Integrated Circuits 1 00:00:00.000 --> 00:00:01.920 Logic families. 2 00:00:01.920 --> 00:00:08.800 Question. Which of the following digital logic families has the lowest power consumption? 3 00:00:09.700 --> 00:00:12.340 Answer. CMOS. 4 00:00:12.940 --> 00:00:22.620 Question. Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply? 5 00:00:23.520 --> 00:00:30.160 Answer. The input switching threshold is about half the power supply voltage. 6 00:00:30.760 --> 00:00:34.430 Both CMOS advantages come from the same design. 7 00:00:34.430 --> 00:00:49.188 The threshold sitting at half the supply gives roughly half the supply as noise margin in both directions, far more than TTL's fixed thresholds, which sit low and give an asymmetric margin. 8 00:00:49.188 --> 00:00:55.668 Question. Which of the following is an advantage of BiCMOS logic? 9 00:00:56.568 --> 00:01:05.768 Answer. It has the high input impedance of CMOS and the low output impedance of bipolar transistors. 10 00:01:06.368 --> 00:01:22.069 BiCMOS uses CMOS for the input stages and bipolar for the outputs, taking the better half of each: high impedance where you want to not load the driver, low impedance where you want to drive a load hard. 11 00:01:22.069 --> 00:01:23.848 Tri-state and pull-ups. 12 00:01:23.848 --> 00:01:28.248 Question. What is tri-state logic? 13 00:01:29.148 --> 00:01:36.348 Answer. Logic devices with 0, 1, and high-impedance output states. 14 00:01:36.948 --> 00:01:55.388 The third state is disconnected, high impedance, neither driving high nor low. It is what lets many devices share one bus: all but one hold their outputs in the high-impedance state, so exactly one drives at a time. 15 00:01:55.388 --> 00:02:01.268 Question. What best describes a pull-up or pull-down resistor? 16 00:02:02.168 --> 00:02:14.528 Answer. A resistor connected to the positive or negative supply used to establish a voltage when an input or output is an open circuit. 17 00:02:15.128 --> 00:02:33.004 An undriven CMOS input floats and picks up noise, switching randomly and drawing current. A pull-up or pull-down gives it a defined level. This is also what makes a tri-state bus behave when nothing is driving it. 18 00:02:33.004 --> 00:02:35.270 Comparators and hysteresis. 19 00:02:35.270 --> 00:02:43.390 Question. What happens when the level of a comparator's input signal crosses the threshold voltage? 20 00:02:44.290 --> 00:02:49.250 Answer. The comparator changes its output state. 21 00:02:49.850 --> 00:03:04.530 A comparator is an op-amp used without feedback: its output slams to one rail or the other depending on which input is higher. It turns an analogue level into a logic level. 22 00:03:04.530 --> 00:03:09.850 Question. What is the function of hysteresis in a comparator? 23 00:03:10.750 --> 00:03:17.550 Answer. To prevent input noise from causing unstable output signals. 24 00:03:18.150 --> 00:03:29.076 Without hysteresis, an input sitting near the threshold with a little noise on it makes the output chatter, many transitions where one was intended. 25 00:03:29.076 --> 00:03:42.290 Hysteresis moves the threshold depending on the current output state: once the output has gone high, the input must fall appreciably below the original threshold to bring it back. 26 00:03:42.290 --> 00:03:57.054 That gap swallows the noise, and one clean transition results. This is what a Schmitt trigger is, and it is why squaring up a noisy signal needs one rather than a plain comparator. Programmable logic. 27 00:03:57.054 --> 00:04:05.654 Question. What is used to design the configuration of a field-programmable gate array (FPGA)? 28 00:04:06.554 --> 00:04:11.314 Answer. Hardware description language (HDL). 29 00:04:11.914 --> 00:04:25.049 An FPGA is a fabric of configurable logic. You describe the behaviour you want in an HDL, Verilog or VHDL, and a tool synthesises a configuration. 30 00:04:25.049 --> 00:04:40.974 This is how modern SDRs are built: the DSP chain from the circuits module is HDL running in an FPGA, which is why the same hardware can gain new modes through a firmware update. 31 00:04:40.974 --> 00:05:00.130 Figure E6-3. This question refers to one of the exam's circuit diagrams, which you will need to look at in the written lesson. Three symbols the pool asks for: Symbol 2: NAND gate. Symbol 4: NOR gate. 32 00:05:00.130 --> 00:05:17.945 Symbol 5: NOT (inverter). Reading gate symbols is two observations: Shape gives the base function. A flat-backed D is AND; a curved-back shield is OR; a triangle is a buffer or inverter. 33 00:05:17.945 --> 00:05:37.197 A small circle (bubble) on the output inverts it. AND plus bubble is NAND; OR plus bubble is NOR; buffer plus bubble is NOT. Two rules, six symbols. Check yourself. Several devices share one data line. 34 00:05:37.197 --> 00:05:55.300 What output type do they need, and what holds the line when none is driving? Your comparator chatters on a slowly-changing input. What does it need? Which shape and marking make a NOR gate? 35 00:06:01.300 --> 00:06:15.025 Tri-state outputs, so all but one sit at high impedance, plus a pull-up or pull-down resistor to define the line when nothing drives it. Hysteresis, a Schmitt trigger. 36 00:06:15.025 --> 00:06:25.463 It separates the two thresholds so noise cannot cause repeated transitions. A curved-back OR shape with a bubble on the output.