WEBVTT NOTE Digital Circuits and Logic 1 00:00:00.000 --> 00:00:19.022 The three multivibrators. One family, three members, distinguished by how many stable states they have. Circuit, Bistable (flip-flop); Stable states, two; Behaviour, stays where you put it. 2 00:00:19.022 --> 00:00:32.610 Circuit, Monostable (one-shot); Stable states, one; Behaviour, switches temporarily to an alternate state for a set time, then returns. 3 00:00:32.610 --> 00:00:43.480 Circuit, Astable; Stable states, none; Behaviour, continuously alternates between two states, an oscillator. 4 00:00:43.480 --> 00:00:47.920 Question. Which circuit is bistable? 5 00:00:48.820 --> 00:00:51.460 Answer. A flip-flop. 6 00:00:52.060 --> 00:01:03.780 The names say it: bi-stable has two stable states, mono-stable has one, a-stable has none. Dividing frequency. 7 00:01:03.780 --> 00:01:10.242 Question. Which of the following can divide the frequency of a pulse train by 2? 8 00:01:11.142 --> 00:01:13.782 Answer. A flip-flop. 9 00:01:14.382 --> 00:01:25.502 A flip-flop changes state on each input pulse, so it takes two input pulses to produce one complete output cycle, division by two. 10 00:01:25.502 --> 00:01:32.982 Question. How many flip-flops are required to divide a signal frequency by 16? 11 00:01:33.882 --> 00:01:36.358 Answer. 4. 12 00:01:36.958 --> 00:01:56.958 Each stage halves, so n stages divide by 2ⁿ. 2 to the power of 4 = 16, so four. Same arithmetic as the 3-bit counter in the General track, and the same as the decibel doublings, powers of two keep appearing. 13 00:01:56.958 --> 00:02:01.798 Question. What is the function of a decade counter? 14 00:02:02.698 --> 00:02:08.938 Answer. It produces one output pulse for every 10 input pulses. 15 00:02:09.538 --> 00:02:28.296 Division by ten, which needs four flip-flops plus logic to reset at ten rather than sixteen. The gates. Gate, AND; Output, 1 only if all inputs are 1. Gate, OR; Output, 1 if any input is 1. 16 00:02:28.296 --> 00:02:46.856 Gate, NAND; Output, 0 only if all inputs are 1. Gate, NOR; Output, 1 only if all inputs are 0. Gate, XOR; Output, 1 if inputs differ. Gate, XNOR; Output, 0 if one and only one input is 1. 17 00:02:46.856 --> 00:03:07.302 Two of these are worth reading twice. NAND is AND with the output inverted, so the pool's phrasing, "produces a 0 at its output only if all inputs are 1", is exactly AND's condition with the answer flipped. 18 00:03:07.302 --> 00:03:12.959 XNOR is XOR inverted: it outputs 1 when the inputs match. 19 00:03:12.959 --> 00:03:32.114 The pool states it the other way round, "produces a 0 if one and only one of its inputs is 1", which is the same statement, since exactly one input high is precisely the case where they differ. 20 00:03:32.114 --> 00:03:35.489 Truth tables and logic convention. 21 00:03:35.489 --> 00:03:39.156 Question. What is a truth table? 22 00:03:40.056 --> 00:03:46.358 Answer. A list of inputs and corresponding outputs for a digital device. 23 00:03:46.958 --> 00:03:58.918 The complete specification of a combinational circuit: every input combination, and what comes out. Nothing about timing or voltage, just the logic. 24 00:03:58.918 --> 00:04:05.798 Question. What does "positive logic" mean in reference to logic devices? 25 00:04:06.698 --> 00:04:13.223 Answer. High voltage represents a 1, low voltage a 0. 26 00:04:13.823 --> 00:04:27.600 The intuitive convention, and the usual one. Negative logic inverts it, and exists because some technologies switch more efficiently pulling down than pulling up. 27 00:04:27.600 --> 00:04:44.693 Worth knowing that the convention is a choice, because a datasheet using the other one will otherwise read as nonsense. Check yourself. You need to divide a 4 MHz clock to 250 kHz. How many flip-flops? 28 00:04:44.693 --> 00:04:53.622 A two-input gate outputs 0 only when both inputs are 1. Which gate? Which multivibrator is an oscillator? 29 00:04:59.622 --> 00:05:14.568 4 MHz / 250 kHz = 16, so four flip-flops. NAND.. Astable, no stable state, so it alternates continuously.