//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v1.3.16 on Sun May 23 11:19:46 2021
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_resource_texture2d (uint,uint,uint,uint) t0
dcl_uav_typed_texture2d (uint,uint,uint,uint) u0
dcl_input vThreadGroupID.xy
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 8
dcl_tgsm_structured g0, 80, 10
dcl_tgsm_structured g1, 40, 10
dcl_thread_group 8, 8, 1
ishl r0.xy, vThreadGroupID.xyxx, l(3, 3, 0, 0)
iadd r0.xy, r0.xyxx, l(-1, -1, 0, 0)
iadd r1.xy, r0.xyxx, vThreadIDInGroup.xyxx
mov r1.zw, l(0,0,0,0)
ld_indexable(texture2d)(uint,uint,uint,uint) r0.zw, r1.xyzw, t0.zwxy
ushr r1.xyzw, r0.zwzw, l(6, 6, 12, 12)
bfi r1.xyzw, l(6, 6, 6, 6), l(8, 8, 16, 16), r1.xyzw, l(0, 0, 0, 0)
bfi r1.xy, l(6, 6, 0, 0), l(0, 0, 0, 0), r0.zwzz, r1.xyxx
iadd r1.xy, r1.xyxx, r1.zwzz
ushr r2.xyzw, r0.zwzw, l(18, 18, 24, 16)
bfi r0.zw, l(0, 0, 6, 6), l(0, 0, 24, 24), r2.xxxy, l(0, 0, 0, 0)
bfi r1.z, l(8), l(0), r2.z, r2.w
iadd r0.zw, r1.xxxy, r0.zzzw
ishl r1.xy, vThreadIDInGroup.yyyy, l(3, 2, 0, 0)
store_structured g0.xy, vThreadIDInGroup.x, r1.x, r0.zwzz
store_structured g1.x, vThreadIDInGroup.x, r1.y, r1.z
mov r2.zw, l(0,0,0,0)
bfi r3.xyzw, l(3, 31, 1, 1), l(0, 0, 0, 0), vThreadIDInGroup.xyxy, l(8, 0, 8, 8)
ige r0.zw, vThreadIDInGroup.xxxx, l(0, 0, 2, 4)
iadd r4.xyzw, vThreadIDInGroup.yxxx, l(0, 6, 1, 2)
movc r1.zw, r0.zzzz, r4.xxxy, r3.xxxy
movc r0.zw, r0.wwww, r3.zzzw, r1.zzzw
iadd r2.xy, r0.xyxx, r0.zwzz
ld_indexable(texture2d)(uint,uint,uint,uint) r0.xy, r2.xyzw, t0.xyzw
ushr r2.xyzw, r0.xyxy, l(6, 6, 12, 12)
bfi r2.xyzw, l(6, 6, 6, 6), l(8, 8, 16, 16), r2.xyzw, l(0, 0, 0, 0)
bfi r1.zw, l(0, 0, 6, 6), l(0, 0, 0, 0), r0.xxxy, r2.xxxy
iadd r1.zw, r1.zzzw, r2.zzzw
ushr r2.xyzw, r0.xyxy, l(18, 18, 24, 16)
bfi r0.xy, l(6, 6, 0, 0), l(24, 24, 0, 0), r2.xyxx, l(0, 0, 0, 0)
bfi r2.x, l(8), l(0), r2.z, r2.w
iadd r0.xy, r1.zwzz, r0.xyxx
ishl r1.zw, r0.wwww, l(0, 0, 3, 2)
store_structured g0.xy, r0.z, r1.z, r0.xyxx
store_structured g1.x, r0.z, r1.w, r2.x
sync_g_t
ld_structured r0.xy, vThreadIDInGroup.x, r1.x, g0.xyxx
ld_structured r0.zw, vThreadIDInGroup.x, r1.y, g1.xxxy
f16tof32 r0.zw, r0.zzzw
ld_structured r1.zw, r4.z, r1.y, g1.xxxy
f16tof32 r2.xy, r1.wzww
ishl r1.zw, r1.wwww, l(0, 0, 24, 16)
add r0.zw, -r0.zzzw, r2.xxxx
mul r2.z, r2.x, l(0.010000)
lt r0.zw, |r0.zzzw|, r2.zzzz
and r0.xy, r0.xyxx, r0.zzzz
ld_structured r3.xy, r4.z, r1.x, g0.xyxx
add r2.y, -r2.y, r2.x
lt r2.y, |r2.y|, r2.z
and r3.xy, r3.xyxx, r2.yyyy
iadd r0.xy, r0.xyxx, r3.xyxx
ld_structured r3.xy, r4.w, r1.x, g0.xyxx
ld_structured r3.zw, r4.w, r1.y, g1.xxxy
iadd r1.xy, r1.xyxx, l(8, 8, 0, 0)
f16tof32 r3.zw, r3.zzzw
add r3.zw, r2.xxxx, -r3.zzzw
lt r3.zw, |r3.zzzw|, r2.zzzz
and r3.xy, r3.xyxx, r3.zzzz
iadd r0.xy, r0.xyxx, r3.xyxx
ushr r0.xy, r0.xyxx, l(2, 2, 0, 0)
and r0.xy, r0.xyxx, l(0x3f3f3f3f, 0x3f3f3f3f, 0, 0)
ld_structured r5.xyzw, r4.z, r1.x, g0.xyzw
ld_structured r6.xyzw, r4.w, r1.x, g0.xyzw
ld_structured r7.xyzw, vThreadIDInGroup.x, r1.x, g0.xyzw
and r3.xy, r3.wwww, r6.xyxx
and r4.xy, r0.wwww, r7.xyxx
iadd r3.xy, r4.xyxx, r3.xyxx
iadd r3.xy, r3.xyxx, r5.xyxx
ushr r3.xy, r3.xyxx, l(2, 2, 0, 0)
and r3.xyzw, r3.xyzw, l(0x3f3f3f3f, 0x3f3f3f3f, 1, 1)
iadd r0.xy, r0.xyxx, r3.xyxx
ld_structured r1.x, r4.z, r1.y, g1.xxxx
ld_structured r2.w, r4.w, r1.y, g1.xxxx
ld_structured r1.y, vThreadIDInGroup.x, r1.y, g1.xxxx
f16tof32 r1.xy, r1.xyxx
f16tof32 r2.w, r2.w
add r2.w, -r2.w, r2.x
lt r2.w, |r2.w|, r2.z
add r1.xy, -r1.xyxx, r2.xxxx
lt r1.xy, |r1.xyxx|, r2.zzzz
and r2.xz, r5.zzwz, r1.xxxx
and r3.xy, r7.zwzz, r1.yyyy
and r1.xy, r1.xyxx, l(1, 1, 0, 0)
iadd r2.xz, r3.xxyx, r2.xxzx
and r3.xy, r6.zwzz, r2.wwww
iadd r2.xz, r2.xxzx, r3.xxyx
ushr r2.xz, r2.xxzx, l(2, 0, 2, 0)
and r2.xyzw, r2.xyzw, l(0x3f3f3f3f, 1, 0x3f3f3f3f, 1)
iadd r0.xy, r0.xyxx, r2.xzxx
and r2.xz, r0.xxyx, l(255, 0, 255, 0)
utof r4.xy, r2.zxzz
mov r5.x, r4.y
ubfe r6.xyzw, l(8, 8, 8, 8), l(8, 16, 8, 16), r0.xxyy
ushr r0.xy, r0.xyxx, l(24, 24, 0, 0)
utof r0.xy, r0.xyxx
utof r6.xyzw, r6.xyzw
mov r5.yz, r6.xxyx
mov r4.yz, r6.zzwz
mov r5.w, r0.x
mov r4.w, r0.y
movc r0.x, r0.z, l(2), l(1)
and r0.y, r0.w, l(1)
iadd r0.x, r0.x, r2.y
iadd r0.x, r0.x, r3.z
iadd r0.x, r0.x, r0.y
iadd r0.x, r0.x, r3.w
iadd r0.x, r0.x, r1.y
iadd r0.x, r0.x, r1.x
iadd r0.x, r0.x, r2.w
itof r0.x, r0.x
div r0.x, l(9.000000), r0.x
mul r0.x, r0.x, l(0.00709219836)
mul r2.xyzw, r0.xxxx, r5.xyzw
mul r0.xyzw, r0.xxxx, r4.xyzw
mad r0.xyzw, r0.xyzw, l(63.000000, 63.000000, 63.000000, 63.000000), l(0.500000, 0.500000, 0.500000, 0.500000)
ftou r0.xyzw, r0.xyzw
mad r2.xyzw, r2.xyzw, l(63.000000, 63.000000, 63.000000, 63.000000), l(0.500000, 0.500000, 0.500000, 0.500000)
ftou r2.xyzw, r2.xyzw
ishl r2.yzw, r2.yyzw, l(0, 6, 12, 18)
or r1.x, r2.y, r2.x
or r1.x, r2.z, r1.x
or r1.x, r2.w, r1.x
or r2.xzw, r1.zzzz, r1.xxxx
and r1.x, r1.w, l(0xff000000)
ishl r0.yzw, r0.yyzw, l(0, 6, 12, 18)
or r0.x, r0.y, r0.x
or r0.x, r0.z, r0.x
or r0.x, r0.w, r0.x
or r2.y, r1.x, r0.x
store_uav_typed u0.xyzw, vThreadID.xyyy, r2.xyzw
ret
// Approximately 0 instruction slots used
