//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v1.3.16 on Sun May 23 13:11:03 2021
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_resource_structured t0, 4
dcl_resource_buffer (uint,uint,uint,uint) t1
dcl_uav_structured u0, 4
dcl_input vThreadGroupID.x
dcl_input vThreadIDInGroup.x
dcl_temps 40
dcl_resource_texture2d (float,float,float,float) t125
dcl_tgsm_structured g0, 4, 3
dcl_thread_group 64, 1, 1

ld_indexable(texture2d)(float,float,float,float) r25.xyzw, l(0, 0, 0, 0), t125.xyzw
ld_indexable(texture2d)(float,float,float,float) r26.xyzw, l(2, 0, 0, 0), t125.xyzw

ult r0.x, vThreadIDInGroup.x, l(3)
if_nz r0.x
  imad r0.x, vThreadGroupID.x, l(3), vThreadIDInGroup.x
  ld_indexable(buffer)(uint,uint,uint,uint) r0.x, r0.xxxx, t1.xyzw
  store_structured g0.x, vThreadIDInGroup.x, l(0), r0.x
endif
sync_g_t
ld_structured r0.x, l(0), l(0), g0.xxxx
ld_structured r0.y, l(1), l(0), g0.xxxx
ld_structured r0.z, l(2), l(0), g0.xxxx
and r1.x, r0.x, l(255)
ubfe r1.yz, l(0, 8, 8, 0), l(0, 8, 16, 0), r0.xxxx
ushr r0.x, r0.x, l(24)
iadd r2.x, r0.x, -r1.x
and r0.x, r0.y, l(255)
iadd r2.y, r0.x, -r1.y
ubfe r0.x, l(8), l(8), r0.y
iadd r2.z, r0.x, -r1.z
ushr r0.x, r0.y, l(16)
imad r0.x, r0.x, l(256), vThreadIDInGroup.x
itof r0.yw, r1.xxxy



div r3.xy, l(1.000000, 1.000000, 1.000000, 1.000000), r0.ywyy



mul r1.w, r3.y, r3.x
mov r4.y, l(0)
mov r5.x, r0.x
mov r5.y, l(0)
loop
  uge r2.w, r5.y, l(4)
  breakc_nz r2.w
  utof r2.w, r5.x
  add r2.w, r2.w, l(0.500000)
  
  
  
  mul r3.y, r1.w, r2.w
  round_ni r3.y, r3.y
  mul r3.z, r0.y, r3.y
  mad r2.w, -r3.z, r0.w, r2.w
  mul r3.z, r3.x, r2.w
  round_ni r3.z, r3.z
  mad r2.w, -r3.z, r0.y, r2.w
  ftoi r6.x, r2.w
  ftoi r6.yz, r3.zzyz
  iadd r3.yzw, r2.xxyz, r6.xxyz
  ult r7.xyz, r3.yzwy, l(64, 64, 64, 0)
  and r2.w, r7.y, r7.x
  and r2.w, r7.z, r2.w
  ult r6.xyz, r6.xyzx, r1.xyzx
  and r4.z, r6.y, r6.x
  and r4.z, r6.z, r4.z
  and r2.w, r2.w, r4.z
  if_nz r2.w
    iadd r2.w, r5.x, r0.z
    ld_structured_indexable(structured_buffer, stride=4)(mixed,mixed,mixed,mixed) r2.w, r2.w, l(0), t0.xxxx
    ishl r3.zw, r3.zzzw, l(0, 0, 6, 12)
    iadd r3.y, r3.y, r3.z
    iadd r4.x, r3.y, r3.w
    atomic_or u0, r4.xyxx, r2.w
  endif
  iadd r5.xy, r5.xyxx, l(64, 1, 0, 0)
endloop
ret
// Approximately 0 instruction slots used
