`timescale 1ns / 1ps
module Sync_Rst_TWO_Input_Adder(Clk,Rst,A,B,AdditionOUT,AdditionOUT1);

	//Parameters must come here now until may
	parameter ComputeDataWidth = 16;
	
	input	                                          Clk,Rst;
	input 			signed	[ComputeDataWidth-1:0] 	A,B;
	output 	reg	signed	[ComputeDataWidth-1:0] 	AdditionOUT,AdditionOUT1;
	
	wire  [ComputeDataWidth-1:0] 	PostAdd;

	//Perform the addition
	
	generate 
			begin : Adding
				assign PostAdd = A + B;
			end
	endgenerate
	
	always@(posedge Clk)
		begin
			if(Rst)
					AdditionOUT	<= 16'b0;
			else
					AdditionOUT	<= PostAdd;
		end
		
		always@(posedge Clk)
		begin
			if(Rst)
					AdditionOUT1	<= 16'b0;
			else
					AdditionOUT1	<= PostAdd;
		end
endmodule