Limits Management Hardware - DCVS

The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick
changes in thermal limits. The hardware responds to thermal variation amongst
the CPUs in the cluster by requesting limits on the clock frequency and
voltage on the OSM hardware.

The LMH DCVS driver exports a virtual sensor that can be used to set the
thermal limits on the hardware. The thermal zone is not capable of reading out
a temperature.

Properties:

- compatible:
	Usage: required
	Value type: <string>
	Definition: shall be "qcom,msm-hw-limits"
- interrupts:
	Usage: required
	Value type: <interrupt_type interrupt_number interrupt_trigger_type>
	Definition: Should specify interrupt information about the debug
			interrupt generated by the LMH DCVSh hardware. LMH
			DCVSh hardware will generate this interrupt whenever
			it makes a new cpu DCVS decision.

Example:

	lmh_dcvs0: qcom,limits-dcvs@0 {
		compatible = "qcom,msm-hw-limits";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	};

