06.09.2014
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IFTLE has been sent a few messages asking for further details on the Hybrid memory cube production. Micron has announced that they will be manufacturing the memory layers and have contracted with IBM to manufacture the logic layer.
Looks a lot like the front end heavy weights Applied, LAM and TEL are going to buy up all the pieces they need to become the 3 heavyweights in packaging and 3D. A significant portion of the panels time was spent discussing current and future interposer sourcing.
During his conference presentation Amkors Huemoeller indicated that they would not be manufacturing interposers and their search of the industry for sources  indicated that only 3 players were close to being ready to deliver interposers that wee useful to Amkor, namely TSMC, UMC and GlobalFoundries.
All 3 of the foundry panelists indicated that they will be commercializing fine featured interposers although as we stated only TSMC and IBM had announced small volume product production has been initiated. TSMCs Yu indicated that they have made their thoughts clear in the past few months and it can be found clearly delineated on their web page. When asked about supplying memory needs, Yu indicated that they would also handle that by having partnerships in place to supply the required memory although these partners were not identified. When asked for their positions, UMC and Global Foundries indicated a preference to work under the open ecosystem model where chips from various vendors could be stacked and assembled by OSAT partners.
Amkor’s Huemoeller indicated that foundries would be supplying interposers and they [ the OSATS] would be assembling them.


When asked for their opinion on the current status of design tools all 3 of the foundries indicated that current design tools are adequate to move forward.
In terms of test strategies UMC would like to see some better standardization in the test area while Yu of TSMC drew a chuckle from the crowd when he noted that test needed to be minimized. Rumors abound that TSMC is designing the apple A6 processor for ipad and iphone with 3D TSV.
When asked about timing for the expected HVM of wide IO memory stacks for tablets, Qualcomm responded probably 2013 and Hynix responded maybe 2015. Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, but the primary obstacle facing development of IVRs is integration of power inductors. There have been rumors out there that IBM would be applying with their 3D technology in their upcoming Power7 devices. David Fick of the University of Michigan showed Centip3De another processor fabbed by Tezzaron. In general, commercial DRAM shows large process variation from chip to chip, which causes address access time variation (tAC). TI’s Mark Gerber, a key player in bringing up their Cu pillar technology at Amkor addressed 3D packaging technology for next generation devices.
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If the item comes direct from a manufacturer, it may be delivered in non-retail packaging, such as a plain or unprinted box or plastic bag. In the event that the contract is terminated, a refund of the whole or part of the purchase price is only made against the return of the goods received. Nexx advanced deposition equipment, including electrochemical deposition (ECD) and physical vapor deposition (PVD) tools will be added to the TEL line of products aimed at back end packaging applications and 3DIC. Altera and Nvida have also announced similar high density interposers for future use as have other graphics chip makers. If these lines are not in place now, is it easonable to think that products using them be qualified and in mass production within the next 24 months ?
During his plenary lecture Yu once again indicated that fabrication of chips on interposers was not as easy as making prototypes makes it look and they strongly favored controlling and being responsible for the full process.


Their presentation at ISSCC may be the first look that we are getting at their early designs for processors stacked with cache memory using TSV technology. A 3-D IC stack using 128 ARM Cortex M3 cores and 256 Mbytes of stacked DRAM operating at near threshold voltage. Mark broke out current FC interconnect technologies into the following 4 categories indicating that fine pitch gold stud bumping was confined mainly to Japan. If you reside in an EU member state besides UK, import VAT on this purchase is not recoverable.
This is conditional upon the goods being sent back in an unused condition such that they can be resold as new, and if possible in their original packaging. After drilling, a conformal oxide is deposited, the barrier and seed layers are sputtered in, the copper fill is plated in, and any excess copper is CMP’d off. During Q and A Cook of Ziptronix offered that she thought their technology was ready and simply awaiting the commitment of a significant player. Similarly no one would offer up comment about who would be supplying Sony who announced that they would require TSV interposers for their next Playstation upgrade.
Implementation of DVFS requires voltage regulators that can provide independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. The module has an un-thinned cache layer and a thinned core layer with WB connecting to TSV on the backside.
According to Samsung the technology would enable manufacturers of mobile and consumer electronics devices to achieve better electrical performance and design slimmer and high-performance handset designs that provide improved battery time. Consolidation will continue because with fewer and fewer players moving to 22 nm and beyond packaging is a natural evolution for some of these big front end equipment vendors.
In the case of articles which are affected by signs of use, or whose packaging is damaged, an appropriate charge is made by us for their decrease in value.
The announced that the technology would enter mass production in 2007, for NAND Flash packages initially. Each backside metal landing pad (56 x 56µm2) is wire bonded to the packaging substrate.
While it is desirable in mobile DRAM to exclude the DLL because of the power cost , TSV stacked DRAM for high-speed operation partially adopts a DLL in the master die (driver circuitry) .



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