Figure 1 shows the process flow for carrier wafer processing as it is implemented on the EVG820 lamination system.
Advantages of tape punching compared to the cutting technologies (laser and blade cutting) are better edge quality for minimum interference with the bonding and back-grinding process, no carrier edge degradation through cutting blades, almost no wear of the punching module components (punch  and die-plate) and more flexibility in tape dimension and shapes. Figure 3 shows the debonding process flow for thin wafers temporarily bonded with thermal release adhesive tape or UV-release adhesive tape as implemented on the EVG850DBL automated debonding system for tapes. Figure 2: The tape punching process enables tailored tape geometry according to the notch specification.
This year’s IMPAS Device Packaging Conference in Ft McDowell, AZ had a series of excellent keynote talks.
Molded FC die on thin core or coreless substrates are approaching 750um thick and warpage issues are becoming significant. Thinner packages require thinner EMC above the die which results in increased warpage and requires EMC with higher mold shrinkage and higher modulus. Having reached a core CTE of 3, reduction in substrate core CTE is no longer an option so the industry is turning to develop materials of increased modulus. Brandon Prior of Prismark continued on the theme of “Mobile packaging and Interconnect trends.” Their analysis of the Apple 5S smartphone confirms the Qualcomm comments about increased use of WLP as can be seen in the fig below. Those of you that are regular followers of IFTLE know that every once-in-awhile, I’ll stop reviewing the latest technology presentations to try to bring home a point. What triggered IFTLE 185 was a panel session held at the recent IMAPS Device Packaging Conference in Ft McDowell AZ.
It is simply amazing that the assembled group of technical practitioners could not agree on what certain packaging terms mean but….they couldn’t. INTERPOSER – for some reason, be it ignorance, youth or a combination of both, some in the audience continue to believe that the term interposer was invented for 2.5D. All 1st level packages are interposers, The purpose of an interposer is to spread a connection to a wider pitch.
SYSTEM-in-PACKAGE – there was mass confusion on what this meant and what is included in this definition. In the 1990s multiple chip packages, MCMs as they became known, were sets of chips that were connected on high density Si, laminate or ceramic substrates by WB or C4.
3D packaging defines the various ways of stacking chips in the z direction whether it be WB them to a common substrate, package-on-package stacking, embedded chip stacking (in laminate or EMC ) or direct connection with TSV. At one point during Bryan Black’s AMD talk at the conference he said “3D” and the audience interrupted him to ask whether he meant 2.5D. Certainly our microelectronics educations have taught us that larger usually means cheaper, i.e. My point to the audience was that PCB are made in large panels because they can be…higher density BGA substrates are made in much smaller strips because they have to be! I actually have hands on experience at what we called LAP back in 1995-1997, as we had a major DARPA contract to try to manufacture MCM substrates  on a sq 400mm format. Do I think that pursuing high density LAP is a worthy R and D goal ?…certainly, lets just not act like it will be easily accomplished.
Let’s take a look at some of the key presentations from the SEMI Summit that took place in January in Grenoble.
Their response to Interposer TSV formation, front side routing and backside reveal and RDL  issues are shown below.
Miekei Leong , VP TSMC, gave the standard TSMC CoWoS pitch but did offer a definition of their supply chain model where OSATS are now integrated as part of the supply chain.
Eric Beyne of IMEC presented data on a cost breakdown of their 5 x 50µm TSV full flow 3DIC process (without stacking) showing the TSV middle fabrication process and the thin and backside eveal processing are about equivalent in cost. They find that a lot of cost is invested in CMP processing which can be improved by reducing the Cu overburden after TSV fill. Timed for release at RTI ASIP was the announcement that Novati had purchased the Ziptronix facility outside RTP NC.
In addition Tezzarons Patti announced that they were partnering with Invensas on 2.5 and 3DIC assembly. Tezzaron, known for its fine featured TSV showed the following process status and an interesting X section of a W TSV connected at M5. Typical thickness requirements for temporary adhesives are dependent on the interface that is being bonded as shown below.
Both Suss and EVG have recently  introduced eximer laser assisted RT debonding which was first introduced by 3M years ago. They report that Apple’s A8 chip will be a package-on-package (PoP) SoC solution comprising processors and mobile DRAM in a single package. IBM fellow Jon Casey examined “System Scaling Technologies and Opportunities for Future IT Workloads and Systems” He notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. Linx consultants looked at “Chemicals and Materials in Semiconductor Devices.” IFTLE notes that an examination of materials suppliers shows that while chip production is moving out of Japan due to cost, Japan still has quite a few of the major materials suppliers on its shores. Like many other prognosticators, Linx points to the cost of 450mm fabs as the main cause of the ever shrinking customer base. An Steegen, Sr VP, IMEC examined “Scaling Beyond 10nm.” She offered the following roadmaps for 3D applications and TSV dimensions. While there is uncertainty in the timing for scaleup of 20 and 16 nodes, by 2020 they expect greater than ? semi sales will come from 32nm and below. They also conclude that low power and low cost will dominate the application space for 32nm or less devices. Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. Their study on the impact of TSVs on the temperature profile in the test chips showed that the presence of the die-die connections, such as Cu or CuSn microbumps or direct Cu-Cu bonds, is more important than the presence of the TSVs itself.
The populated interposer is then mounted on the PWB using Sn-57Bi solder to achieve low temp reflow. IBM Japan reported on the warpage and mechanical stresses generated during chip and interposer assembly processes.
Sequences are each divided into two steps, with either chip joining or interposer joining being the first step. In the chips first sequence, interposer warpage is caused by CTE mismatch between interposer and RDL. The evaluated Von Mises stress on the interposer to substrate solder balls and found the largest stress was developed by the thickest silicon interposer and the lowest on the thinnest glass interposer. For 3D stacking capillary underfilling has clear limits in terms of the gap between die and the bump pitch. For many years PFTLE and IFTLE have been proponents of die thinning for 3D IC stacks because it not only has an effect on the final thickness of the product, but also has a direct effect on the TSV AR.
In this presentation, ST Micro, CEA Leti, Datacon, Disco, and EVG presented two approaches have been investigated for B2F bonding of the thinned die: (1) applying a die attach film (DAF) bonding layer, or (2) using spin coated polymers for the die attach. Using DAF is an acceptable solution but placement accuracy was degraded due to the presence of the DAF under the die and tool clogging by the DAF. Bob Patti of Tezzaron Semiconductor has been touting the merits of 3DIC for longer than most everyone else in our industry.
Tezzaron has always been at the leading edge, offering 2µm pitch W TSV several years ago. Last week Tezzaron took a major step toward alleviating that problem with the announcement that it is acquiring the wafer fabrication facility of SVTC Technologies in Austin, Texas. Gu and co-workers at Qualcomm reported on a memory on logic 3DIC stack consisting of a two-chip-wide IO memory stack bonded to a 28nm logic chip. Negligible shift in electrical parameters are observed after optimizing TSV formation and determining the need for a 5µm keep-out zone (KOZ). In this latest presentation, Banijamail and co-workers examine the reliability of their 2.5D Virtex-7 H580T which consists of a transceiver chip and two FPGA slices. Different substrate sizes and designs, lid designs, lid materials, and underfills were examined to minimize warpage and maximize microbump and c4 bump reliability. IFTLE has detailed many times how Applied Materials is making 3DIC a focus area for its equipment business. Eaton and co-workers from Applied Materials now present process detail on how scallop-free TSV can be etched in their Silva etch chamber.
Many of you may be wondering why IFTLE has recently been paying so much attention to the Apple A6 processor. We have mentioned before that the A6 is the odds-on favorite to be a major driver for bringing 3DIC (or at least 2.5DIC into high volume manufacturing). Since the introduction of the iPhone in 2007, there have been five generations of iPhone models, each one improving on the technology used for the preceding model. Apple has partnered with Samsung for every generation of their application processors but recent Apple-Samsung lawsuits over patents related to competing handsets has lent credence to the rumors that Apple was going to switch production to TSMC.
Thus, multiple trusted sources agree that the A6 looks like it is being manufactured by Samsung 32nm technology. TSMC has announced a goal of getting its 28nm supply and demand into balance by the end of this year. At a recent investment conference, Qualcomm, maker of baseband chips and application processors (like Snapdragon) for smartphones and tablets, reported that it has had trouble meeting customer demand and is trying to ramp the supply as quickly as possible. Bloomberg reports that Apple and Qualcomm have made investment offers of more than $1B each, in order to set aside production capacity exclusively for them — but have been rebuffed by TSMC [link]. The Bloomberg report says the smartphone chip market that is worth US$219.1 billion worldwide.
At present Apple relies on Samsung for its leading-edge A5 processor — but we all know about the high-profile legal dispute with Samsung over smartphones patents, and how Apple has been reported to be working with TSMC (Hsinchu, Taiwan) to bring up a 28nm A6 processor. Apple may have won the recent Samsung suit concerning smartphones, but it appears that the joke was on them!
In this case I think I know who the rhino is — and I think the rhino has decided to use bug spray and get the birds off his back! The bulb uses 3M’s multilayer optical film, adhesives, and heat-management technology. IFTLE has gone into great detail to show that it is the bulb that matters, not the expected life of the LED chip. As I shook my head in disbelief that this scam of the American public was continuing unabated, with no corrective information coming from the DOE or any other Government agency [yes that was said tongue in cheek], I got a collect call from old friend Lester Lightbulb.
While I had him on the phone I thought you, the readers of IFTLE, would appreciate a direct interview with Lester. IFTLE: Lester, of course we know that CFL and you are not related, we were just trying to link you, CFL and LED as part of the interior lighting family. Lester: Mercury has long been recognized worldwide as a health hazard because its accumulation in the body can damage the nervous system, lungs, and kidneys, posing a particular threat to babies in the womb and young children. Tests on hundreds of Chinese employees found dangerously high levels of mercury in their bodies and many have required hospital treatment, according to local health officials in the cities of Foshan and Guangzhou.
Is anyone who is buying a previously owned home thinking about whether the carpet has been contaminated with mercury? Lester: No, none of us are, but the electric utilities are taking steps to reduce mercury emissions from power plants as part of ongoing pollution prevention programs.
Lester: Anyway, my point is that instead of justifying toxic quicksilver light bulbs by pointing a finger at how toxic power generation is, why not continue to use safe, non-toxic, incandescent light bulbs and work on cleaning up the effluent from our power plants? Lester: The basic problem is that quicksilver bulb lifetime is impacted by how often the bulbs are turned on and off and their use temperature.
Homeowners will also be faced with the expensive requirement to replace all non-ventilated light fittings with new ones that have sufficient airflow to maintain a safe temperature for CFL use.
Any potential saving in energy bills is gone … for quite a few years, until the cost of the fittings and their installation is amortized.
Reports in Taiwan are that TSMC lost the chance for making Apple A3 processors to Samsung because of its lack of the capability to package and test the chips. The Thin Wafer Handling Task Force is focused defining thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing. The Bonded Wafer Stacks Task Force is near completion of its SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack and SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks. Current wafer standards do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits.

The Middle-End Task Force is focused on the middle-end processes on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. CMOS image sensors are used in a wide range of Sony products, including digital cameras, digital camcorders, DSLR cameras and Android based smartphones. At the recent Semicon West, Suss, which supports all commercially available temporary bonding solutions, held their annual 3D workshop. IMEC is moving their standard process from 5 um in 50 um thick silicon to 3 um in 50 um thick silicon. The former is exemplified by the now infamous Xilinx FPGA interposer development which Amkor is in the process of assembly scaling up. With the help of 3M and IBM I have made contact with Herve Gindre, division vice president at 3M Electronics Markets Materials Division, and Bernie Meyerson VP of research at IBM, to clarify exactly what is being proposed. Digitimes reports that TSMC has undertaken in-house high-end packaging of ICs, produced by its foundry processes, for fabless IC design houses in the US and Europe [link]. At the last several TSMC spring Technology Symposia, in Silicon Valley, TSMC announced plans to expand its efforts in IC packaging. Indications are that TSMC can generate gross margins of 50-60% for foundry services but even with their higher prices only 20-30% for packaging services. Whatever your take is on this new information, it is clear that TSMC is slowly but surely moving into what was before a clearly defined packaging and assembly space.
Two other readers sent me email indicating that my concern over the life expectancy of the components in the bulb were well-placed, and that this certainly was not taken into account by Philips in their lifetime claims. This entry was posted in Uncategorized on September 10, 2011 by insights-from-leading-edge. Samsung has just announced the development of 32 GB DDR3 memory module (RDIMMs) using their 3D TSV packaging technology and their advanced 30 nm 4 Gb DDR3 chips. GLOBALFOUNDRIES and Amkor have announced that they have entered into a strategic partnership to develop packaging solutions for advanced silicon nodes. As we have detailed many times in IFTLE, the move to advanced technology nodes has caused  packaging and interconnect solutions to become increasingly important. Gartners estimation of total capacity availability by node and year is shown below followed by the fact that the finer feature chips are the ones driving packaging advances. The TechXSpot session 3D in the deep submicron era was led by Jie Xue, Cisco Systems and Gamal Rafai-Ahmed, AMD . To reduce the impact of TSV stress on devices, a keep-outzone is defined around the TSV structure. Jon Greenwood of GlobalFoundries addressed backside integration and supply chain challenges. They offer the following as what they view is becoming the standard TSV and backside processing flow.
In terms of supply chain they envision the foundry plus vs the OSAT plus vs the third party models as shown below where the manufacturing solution, reliability and warranty ownership is in the hands of the foundry, the OSAT or the 3rd party respectively. Finally GF points out that while the substrate industry is stable and reliable, interposer delivery is a complete unknown. Compact fluorescents have been fully commercial now for several years and also use significantly less power than our friend Lester. Popping open a CFL reveals a small PCB with ~ 20 components (mainly passives) loaded on its top surface. I personally would have an on off cycle where the bulb was switched off and then back on every 3 hours to mimic the daily use because we all know that bulbs usually burn out in the power on cycle, not while they are lit (at least that’s true for incandescants). Below shows what I was able to find selling at my local Home Depot (An American hardware store). After alignment and temporary bonding Beyne recommends the use of use of in-line metrology to allow for wafer rework if necessary.
Strid pointed out that standard pad locations will be required for vendor interchangeability and that standard materials specs for pads are needed in terms of materials, thickness and flatness.
Stefan Lutter , Bonder Project Mgr for Suss, discussed equipment and processes for temporary de-bonding. Thinned wafer on carrier mounted to flex frame are fed to these modules and thinned wafer on flex frame and detached carrier are generated.
Dry film adhesive tapes usually consist of a backing foil with adhesive films plus protective liners on both sides. In case that edge trimming of the device wafer is being used, a reduced tape diameter can be used in order that no openly exposed tape interferes with backside processes after thinning. We’ll first take a look at some of those and then look at several key presentations from the conference. Since the battery and the screen are not shrinking chip packaging and the substrate board must make up the difference. Although he added that there was no clear infrastructure answer for where interposers will be coming from. A good panel session experts discuss controversial topics but that is not exactly what happened here.  This panel session degraded into a school yard verbal battle (panel members and audience) over what certain terms mean.
In the early 2000’s it became vogue to call these system-in-package as industry focus became delivering functions for portable devices in separate modules. Whether its side by side, stacked, through hole or embedded, these multiple chip solutions are all versions or categories of SiP. Check out my chapter “High Density, Large Area Processing (LAP) in the Multichip Module Technology Handbook [link]. It is focused on commercial 3DIC technology and applications and is always a good indicator for the status of the industry.
Tezzaron had been a licensee of the Ziptronix’s direct bonding technologies, ZiBond™ and DBI® and they now have control of the Ziptronix facility to serve as a second source for their processing [link]. In the past this has been a treasure trove of information on how and why the IC industry is making the moves that it does.
Business Strategies (IBS) who in the past have contributed significant data to IFTLE arguments that 3DIC makes economic sense in light of the other scaling options, addressed They indicated that growth in 2013 was mainly due to an increase on memory pricing. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. ICECool Fundamentals is, thus, the first step toward achieving the system performance goals of the ICECool program and will develop the fundamental building blocks of intrachip and interchip evaporative microfluidic cooling.
IFTLE will keep you informed as the winners are announced and their proposed thermal solutions become public. This limits high density integration and therefore shifts focus onto pre applied underfill where the material is dispensed on the landing die before stacking. In order to obtain good step coverage, die are singulated at 45° to provide edge slope. The best solutions were found to be: (a) 200-240 C LTO in combination with the BCB adhesive layer, or (b) spray coating of positive, photo WPR 5100 from JSR.
Being ahead of the industry, frankly, they have had issues working through the regular supply chain. No change in bump resistance is seen after 1000 hrs at 150°C and 1000 cycles of temp cycling.
Control of these variables resulted in packages that met JEDEC warpage spec and minimized BGA fatigue.
This expansion also causes stresses to be generated which in turn require a KOZ (keep-out zone) to be defined so said stresses do not negatively impact the transistor electrical performance.
They chose optical imaging and AFM as their methods of choice and micro raman spectroscopy to determine post-CMP anneal stress. In agreement with the previous studies by Sibelrud, they find that plating bath chemistry has a major impact on protrusion. Even though my link was to Google-Nexus, not some crazy blogger with no credibility, I should have known better. The emergence of cloud computing is also expected to help accelerate the adoption of 2.5D and 3D TSV chips, he believes.
Circulating rumors suggest that Qualcomm has looked for 28nm capacity at UMC and GF but has returned to TSMC since things were even worse at its competitors.
According to the Taiwan Economic News, TSMC’s 28nm capacity is now running at 100,000 wafers a month, up from the 25,000 wafers a month capacity in Q2.
The report said that Apple’s proposal was aimed at securing an alternative supplier to Samsung for chips for its iPhones and iPads, while Qualcomm, leading supplier of application processors to the rival Android platform, needs to boost supply as shortages have impacted its earnings. The article went on to say that the bulb, which looks like a traditional incandescent, has a 25-year lifespan (at three hours of use per day) and a $25 price tag.
If any of the components of the bulb are not rated for a 25-year lifetime the bulb should not be rated for this period of time.
As you know Lester is sitting on death row in San Quentin [isn't it fitting that California is the state that incarcerated him]. They are the least environmentally friendly source of light that we can use, which makes it quite ironic that those who claim they are trying to save the environment are about to eradicate me and use him. At the Nanhai Feiyang lighting factory in Foshan tests found 68 out of 72 workers were so badly poisoned they required hospitalization. In 1990, EPA was given authority to control mercury and other hazardous air pollutants from major sources of emissions to the air. In fact, existing control technologies for sulfur dioxide (SO2), nitrogen oxides (NOx), and particulate matter have reduced power plant mercury emissions by roughly 40 percent already. Optimal use for a fluorescent light is to be left on all the time at temperatures between 50-80°F. Because such fittings must be installed by a licensed electrician (in most countries), this is another expense that is usually ignored. There is also the enormous waste of replacing perfectly good light fixtures with new ones, so the environmental impact is also negative — probably by a large margin. He is the award-winning lighting designer who helped develop the nation’s first standards for energy-efficient building design. The real areas that should be looked at that would make big gains are in all commercial office buildings. I sincerely hope we can turn things around and get you a pardon, for your good and the good of the country. Reports are that they have hired experts away from ASE, Siliconware and Powertech to fill these vacancies.
TSMC management reportedly now feels confident of securing Apple’s foundry contracts for next-generation processors. SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs). Current standards for shipping are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. In each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present.
The task force’s first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration. Sony has focused on key traditional parameters such as increased pixel counts, improved resolution and higher speed. This can occur by breaking up large pieces of logic into smaller chips and mating on an interposer or breaking up a large monolithic die into functions and mounting on an interposer. VP Meyerson declined to share much detail on timing or technology, which is to be expected since the program hasn’t even started.
This would obviously create competition for Amkor, ASE, SPIL, STATs and other subcontractors. Thus some are questioning why they would expend precious equipment capex on the packaging side.
Thanks for that, because it exposed a flaw in the new software that appears to be blocking comments. The modules can transmit at speeds of up to 1,333 Mbps, a 70 percent gain over preceding quad-rank 32GB RDIMMs (operational speeds of 800Mbps). Packaging techniques are leading to improvements in performance and power-efficiency as well as reduced costs. CMOS BSI sensors BSI sensor technology is being used by Sony and has been announced in video camcorders and digital still camera products by Casio, Nikon, Ricoh, Samsung, JVC and Fujifilm among others.

Walker pointed out that between 1980 and 2010 the number of different packages available on the market has increased from 30 to more than 2200 ! Its probably pertinent to insert at this point that the Xilinx program choose to have TSMC manufacture and FC the interposer and thus chose option #1. While Amkor sees many TSV based products requiring an interposer, they see a severely constrained supply chain which is negatively impacting product proliferation. Basically an incandescent light bulb with a smiley cartoon face on it told kids to remember to shut off the light when not in use and to not to put things into the electrical sockets. Certainly Lester the lightbulb which has been around for more than 100 years obeys that law. Like their tubular precursors, CFLs contain a small amount (typically five mg ) of mercury. Department of Energy has had a competition running to find a viable replacement for the  60-watt incandescent .
In addition, we have publicly said we will use the L Prize money to expand the manufacturing of this product in the United States. This also only indicates to me what the projected light output would be at 25K hrs, not that the bulb will be functional after 25K hrs.
Increased price of energy makes them look better and failure of any of the components in the bulb will make their relative price increase significantly. Changing 4B bulbs to CFLs in a year will increase the mercury released to the environment by ~ 20,000 Kg with much of this concentrated in the urban areas where our population is concentrated. To be exact we are talking USP 6,052,287 filed in Dec of 1997 and issued in April of 2000 which gives it another 6 years of life.
Beyne points out that right now silicon carriers are favored over glass because the glass, while transparent which allows for laser based optical debonding techniques, must be CTE matched to silicon over a large temperature range; ground to tight TTV specification (high cost ?) and has a negative effect on plasma based post grinding backside processes due to its low thermal conductivity.
The technology uses a porous vacuum chuck to hold the thin device wafer that is mounted on tape and a flexible plate with vacuum grooves and debond initiator to peel-off the carrier. Both adhesive films are debondable, but different debonding mechanisms are used for either side. The wafer notch is punched out simultaneously, which enables full support of the thin wafer in the notch area, while avoiding openly exposed tape around the notch (Figure 2).
Aligned lamination enables full support of the thin wafer in the notch area, while avoiding openly exposed tape around the notch. If you really want to follow the chronology of the discussion you can here [Advanced Packaging Alphabet Soup Creates Chaos for IMAPS 3D Panel]. This is clearly shown in the Infineon slide that they have been showing for nearly 20 years. I think some of these disagreements come from the fact that corporations do not divide things up in their business units based on definitions so all things SiP may not be in the same business unit and this influences their thinking.
Need more history on MCMs try the Multichip Module Technology Handbook [link] which Iwona Turlik and I edited in 1998.
Tong was not trying to create a new nomenclature, he was making a joke that we were not ready for 3D but this silicon interposer with TSV would get us close. This is true as long as the equipment and technology is available to give you high yields, i.e. By the way our program with MMS and others to manufacture high density MCM substrates made for a great magazine cover (see below)…too bad it didn’t yield! 25µm they can be stacked B2F without TSV and metallized over the edge to make interconnect. Tezzaron will continue the operation of this facility while adding capabilities to assemble its own 3DIC devices.
IFTLE concludes that it is likely that the 2nd-gen A6 will be done in 28nm technology by TSMC similar to the 45nm and 32nm versions of the A5 (as shown in the table above), and this is the point of entry for the TSMC 2.5D technology.
BJ Han, executive vice president and chief technology officer, indicates that their "primary focus has been to develop high-volume TSV technology capabilities that we can offer to customers at cost points that make TSV a viable solution. TSMC’s fab 15 in the Central Taiwan Science Park is said to be ending Q3 with 69,000 28nm wafer per month capacity and will expand that to 135,000 wpm in Q4. Minutes later, Apple CEO Tim Cook received a call from Samsung indicating that over the next week they would be paying the $1 billion dollar fine in nickels. I checked the IFTLE BS meter for the merit of LED lightbulb ads and sure enough they rate just short of outright fraud. For fossil fuel-fired power plants, the amendments required EPA to conduct a study of hazardous air pollutant emissions. It’s claimed that a CFL will last ten times longer than an incandescent [It says so right on the packaging]. Although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry.
Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. January 2012, Sony announced that it had successfully developed a 3D stacked CMOS image sensor complete with TSV. It certainly makes it look like the chips are actually being simply glued together, but if this is 3D stacking with TSV then this would be a chips-last solution, and certainly that cannot be done with more than two layers at a time. GlobalFoundries indicates that they expect to strike similar deals with other companies to create a broader alliance of packaging partners. IFTLE readers know that the adoption of 3D IC stacking of ICs is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. It was just announced that after 18 months of testing the Philips Lighting North America bulb had won the DOE’s $10MM prize.
The new lamp is also brighter than the one marketed now, at 910 lumens versus 800 lumens and reportedly  closer in color to a standard incandescent.
We will do this internally [at Philips facilities] as well as with American partners”[link].
Spectral measurements were taken on each bulb every 100 hrs for the first 3K hrs and every 168 hours (weekly) thereafter. Popping off the phosphor coated covers we see the LEDs mounted vertically on the interior central column on the bulb. I am not convinced that anyone has determined whether all the passive components currently used on these devices will last that long and if they don’t, it will not matter if the bulb was outputting 800 lumens at the time that the bulb failed.
The example that I gave on the slide is EE Times (because it is the most prestigious of the lot) who appropriately referenced the original source (which may I say many others did not do) . If you’re in the business of making or using such interposers, you might want to give this patent a look !
They see the industry trend as moving to the newer room temperature (RT)  release processes. This allows controlled debonding, where the separation between thin device wafer and carrier wafer happens at the interface between device wafer and tape. Bezuk commented that 5 years ago very few of the packages were WLP but now this category accounts for near 50% of the packages IC. While these memory chips are still WB, Prismark stated that they expect performance DDR to go FC at the big 3 memory suppliers and expect 5B units shipped by 2018. Glass interposers not looking like the price will be low enough for mobile products?…don’t worry we can manufacture on LAP lines and the price will come way down. The difference in thermal conductivity between the metallic bonds and the adhesive material is thus two orders of magnitude. Without plasma treatment of the backside and edges, they found 100% of the die broke during the subsequent pick and place operation.
Tezzaron indicates that they will be operating the fab with the same employees in the same location.IMAPS 2012The 45th Symposium on Microelectronics (IMAPS 2012) was held a few weeks ago in San Diego. Thinned die are shipped either on their carrier (OSAT removes the carrier) or after removal from the carrier on a flex frame.
They suggest that copper grown in a tensile stress state is a significant contribution to protrusions after thermal annealing at high temperature. In 1999, EPA estimated that approximately 75 tons of mercury were found in the coal delivered to power plants each year and about two-thirds of this mercury was emitted to the air annually.
It was evidently was on display at the Cadence booth at the recent design automation conference.
SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers. In place of the supporting substrate used in conventional back-illuminated CMOS image sensors, this image sensor stacks  the back-illuminated pixels layer onto chips containing the circuit section for signal processing which facilitates greater functionality and compactness. They are expanding their bumping and wafer-level chip-scale packaging technology and have announced copper pillar bump technology on 100μ bump pitch and will be manufacturing silicon interposers with TSV for 3D stacking.
It is also clear that the ability to deliver end-to-end solutions such as 3D IC for customers will require such partnerships between foundries and OSATS to better enable supply chain management.
Its use in applications from thermometers to automotive and thermostat switches have been banned. Data for the first 7,000 hours of operation were used to predict lumen output of the bulbs at 25,000 hours. The LEDs are mounted on a little PC board which is a bit more complex than the CFL board (tongue in cheek) . The thin wafers are released from the carrier at room temperature after mounting on a film frame.
The tape is laminated with a controlled process, which avoids gas encapsulation in the interface.
Let’s look at some of the 3D and advanced packaging papers presented at this meeting.
Residual mercury in the carpeting has particular significance for children rolling around on a floor, babies crawling, or non mobile infants placed on the floor….
In 2000, the EPA found that regulation of hazardous air pollutants, including mercury, from coal and oil-fired power plants was appropriate and necessary. The new structure is positioned to become the next generation of back-illuminated CMOS image sensors. When a bulb breaks the mercury can be inhaled from the air or can settle into the carpet for future slow release toxicity. Lumen maintenance is predicted to be 99.3% at 25,000 hours, significantly exceeding the 70% L Prize requirement [link]. The large amounts of metal (this is one heavy bulb) are used as the heat sink to conduct the heat away from the LEDs. Blanket UV exposure on the flex frame allows solvent removal of the temporary adhesive without damaging the adhesion to the flex frame tape. Vacuuming up the smaller debris particles in an un-vented room can elevate mercury concentrations over the MAAG in the room and it can linger at these levels for hours. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well.
Jim got interested in this and tells me that he can now find them for both prices in different parts of the country.
In many locations it is already illegal to throw fluorescents out with regular garbage, however recent  recycling data ( Association of Lighting and Mercury Recyclers) estimates a residential mercury bulb recycling rate of a mere 2 percent. Original requirements called for a target retail price of $22 for the first year, $15 for the second year, and $8 in the third year they were offered for sale. The carrier with the laminated adhesive tape is now ready for the temporary bonding process.
You can’t be for supporting mercury pouring into the atmosphere from our electric utilities, can you? Philips has said it plans to offer the bulb for retail sale as soon as early 2012 although reports are that it will sell for ~$60 due to the higher cost of its materials content. The one that I now have installed actually cost me $49.99 since I bought it locally (and still have the receipt). Anyway, my point is not that the price would never come down, but rather how far down it had to come to make purchase of this device a good business decision vs the CFLs.
Both bulbs are still glowing brightly — as well they should, well past my lifetime expectancy if I am to take their marketing propaganda seriously.

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